THE A-TEAM MATHIVATHANI BARATHI MOHAN DINESH UDAYAKUMAR BHARGAV BHAT BHASKAR.

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Presentation transcript:

THE A-TEAM MATHIVATHANI BARATHI MOHAN DINESH UDAYAKUMAR BHARGAV BHAT BHASKAR

CLIENT 1 SERVER 1 CLIENT 2 SERVER 2 SOFTWARE HARDWARE

BUYER 1 COMPANY B CLIENT 1 CLIENT 2 SERVER 2 SOFTWARE HARDWARE STOCK MARKET SCENARIO BUYER 2 COMPANY A SERVER 1

BUYER 1 COMPANY B STOCK MARKET SCENARIO BUYER 2 COMPANY A CUSTOM NETWORK PROCESSOR PAIRS TRADING ALGORITHM

MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ Input Arbiter Output Port Lookup MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ Output Queues Custom Network Processor Incoming Packets

Control Unit FIFO/DATA MEMORY PC ALU Ctrl Branch PC+1 Branch Address Jump Jump Address Thread Scheduler FALL THROUGH FIFO INSTRUCTION MEMORY 1 INSTRUCTION MEMORY 2 REGISTER FILE 1 REGISTER FILE 2 REG_SEL ALUSrcB MemToReg ALU INCOMING PACKETS FROM OUTPUT PORT LOOKUP OUT_FIFO Memory Ctrl Start_write Start_proc Start_read Crypto Engine

Control Unit PC ALU Ctrl Branch PC+1 Branch Address Jump Jump Address Thread Scheduler FALL THROUGH FIFO REG_SEL ALUSrcB MemToReg ALU INCOMING PACKETS FROM OUTPUT PORT LOOKUP OUT_FIFO Memory Ctrl Start_write Start_proc Start_read User Authentication Module Valid Invalid INSTR 1 INSTR 2 INSTR 3 INSTR 4 Packet Header Dst.Port Src.Port Length 0001 XXXX XXXXXXXX XXXX XXXXXXXX n0 port addr n1 port addr n0 val n1 val FIFO/Data Mem Scratch Mem HW ACC.

Latency Comparison – Hardware Vs Software Routers Time in ms No of Bytes per packet

DateTasksStatus 6 th AprilMultithreaded ProcessorCompleted 13 th AprilAnalysis of packet contentsCompleted 20 th AprilSoftware Router DesignCompleted 27 th AprilMimicking Pairs Trading AlgorithmCompleted 27 th AprilImplementation of User AuthenticationIn Progress 27 th AprilImplementation of Rerouting mechanismIn Progress Analysis of achieved resultsYet to start