Conference title 1 A Research-Oriented Advanced Multicore Architecture Course Julio Sahuquillo, Salvador Petit, Vicent Selfa, and María E. Gómez May 25, 2015 Turku, India

EduPar Outline Introduction Proposed course Teaching methodologies Course contents Conclusions

EduPar Introduction Typical Computer Architecture Courses organization – 1 introductory course – >= 1 advanced courses –E.g. Parallel Computer Architectures, Memory subsystems,… Teaching up-to-date topics in advanced courses  key issue to motivate students Main problem: vertiginous technological advances  huge effort is required by the instructor 3

EduPar Introduction Interesting courses are being currently proposed – Research in Parallel Computer Architecture by Onur Mutlu at Carnegie Mellon Instructor profile: wide and active research experience –Key point: some instructor’s papers (recent or not) are discussed at classroom  Contents are being continuously being updated  The effort of preparing the course is not so hard 4

EduPar Proposed Course Advanced Multicore Architectures (AMA) – Inspired in the previous approach – Fully-research oriented approach that tries to –1) provide updated contents –2) capture the students’ interest –3) enable students to research – 2015, UPV, Spain – 16 classes x 2.5 hours = 40h, classroom equipped with PCs

EduPar Proposed course: 5 commandments – 1. Concentrate on few topics and cover them in detail –2. Topics should focus on key components (on multicores) – Cores, caches, and main memory –3. Performance evaluation (for multicores) –4. Instructors highlight for each studied component the hot research topics from both the academia and the industry –5. Select the proper methodology

EduPar Choosing the teaching methodologies Should help to achieve the course goals – Make the course attractive for students – Provide a sound understanding of the studied topics – Enable the students in the research  study few topics Used Teaching methods –Research-oriented lectures – Practical exercises – Realistic labs – Course work 60% 15% 25%

EduPar Teaching methods Lectures –Review & study theoretical concepts  to enable students to the discussion of papers Research-based exercises: problems that students will likely face after graduation –e.g. energy consumption (CACTI), confidence intervals, … –½ hour to 1 hour Lab sessions provide the students with the skills to work on a research simulation framework (academia and industry) –Guided by instructors –2.5 hours Course work: complex implementation in the simulator –Students should show their autonomy  Not guided –20% over the final grade

EduPar Course contents MODULE 0. Course Presentation MODULE 1. Core review and multicores MODULE 2. Performance MODULE 3. Caching MODULE 4. Main Memory

EduPar Module 1. Core review and multicores Topic 1.1. Advanced Microarchitectural Concepts (review) Topic 1.2. Multicore Processors Why Topic 1.3. Multicore Evolution and Design IBM Cell BE 8+1 cores Intel Core i7 8 cores Tilera TILE Gx 100 cores, networked IBM POWER7 8 cores Intel SCC 48 cores, networked Nvidia Fermi 448 “cores” AMD Barcelona 4 cores Sun Niagara II 8 cores Topic Commercial processors Alpha Pipeline: physical register file, ROB, load/store unit -SMT processors (focus: where stalls can rise) -Paper assignment to be discussed the next class -The case of a single-chip multiprocessor -Complexity-effective superscalar processors Topic Bigger cores vs more cores; superscalar complexity -Alternative architectures -Paper discussion Topic 3.3 -Different multicores simple cores, complex cores, etc. -Amdahl’s Law for multicores based on Mark Hill’ talk: Amdahl’s Law in the Multicore Era

EduPar Module 2. Performance Topic 2.1. Performance Evaluation Metrics Topic 2.2. Performance Accounting Architectures Individual Slowdown: quantifies the performance degradation due to multicore execution Unfairness Topic Multicores are not evaluated like single cores  specific performance metrics are required -S. Eyerman and L. Eeckhout, “Restating the case for weighted-IPC metrics to evaluate multiprogram workload performance,” IEEE Comput. Archit. Lett., vol. 99, p. 1, P. Michaud, “Demystifying multicore throughput metrics,” IEEE Com- put. Archit. Lett., vol. 12, no. 2, pp. 63–66, Topic 2.2 -Accounting architectures allow achieve a sound understanding about where performance can be lost -Focus: single-thread, multicores and SMT cores -S. Eyerman et al, “A performance counter architecture for computing accurate CPI components,” in ASPLOS, 2006

EduPar Module 3. Caching Topic 3.1. Advanced Caching: Concepts and Problems Topic 3.2. Advanced Caching: Papers Topic 3.1 -Concepts: outstanding misses support, lock-up free caches, MLP,… -Problems: shared caches, QoS management, sharing vs partitioning Topic 3.2 -Cache partitioning: Utility-based partitioning paper [19] -Insertion policies: The evicted- address filter: A unified mechanism to address both cache pollution and thrashing [20] -Replacement : A case for MLP-aware cache replacement [21] CORE 0CORE 1CORE 2 CORE 3 DRAM MEMORY CONTROLLER L2 cache

EduPar Module 4. Main memory Topic 4.1. Main Memory Organization Topic 4.2. Main Memory Scheduling Topic Bottom-up approach -Cell  cell array  bank  chip  rank  DIMM Topic 4.2 -Row buffer & memory requests queue at the MC -Policies: FCFS, FR-FCFS

EduPar Conclusions The fully-research oriented AMA course has been presented –Methodology: lectures, exercises, labs, and course work It is important to train students on exercises and simulators We should reduce the time devoted to theoretical concepts but... theoretical concepts should be studied in detail Results: some of the course works (o extended versions) have been published in top research conferences like IPDS or PACT Most students of the course have then followed their PhD with us However … it is only applicable for a relatively low number of students

Conference title 15 May 25, 2015 Thanks Gràcies