Signal Integrity Methodology on 300 MHz SoC using ALF libraries and tools Wolfgang Roethig, Ramakrishna Nibhanupudi, Arun Balakrishnan, Gopal Dandu Steven McCormick, Vinay Srinivas, Robert Macys, Dhiraj Sogani, Kevin Walsh

Introduction Signal integrity becomes dominant factor for design closure in 180nm technology and below Conventional design method for SI –multiple point tools for analysis –repair manually or by scripts New design method for SI –Same tool for analysis and optimization –Unified signal integrity library Signal integrity library contents using the Advanced Library Format (ALF) will be explained Results on 333 MHz SoC design will be shown

Conventional crosstalk-aware STA P&R data delay calculation SDF pessimistic! time window calculation Extra delay due to aggressor / victim overlap Refine time windows Time windows accurate? no Do another design iteration yes no STA Timing o.k.? done yes

Issues with crosstalk-aware STA Iterative STA due to Chicken-and-egg problem –To calculate crosstalk-effects on delay, time windows must be known –To calculate time windows, delay must be known Conventional STA can only handle one time window per clock cycle –Pessimistic assumption for crosstalk –Overestimation of multi-aggressor effects New crosstalk-aware STA –Delay and noise calculation integrated in STA –Supports multiple activity windows per clock cycle

New STA with activity windows Multiple activity windows per clock cycle Individual slew rates for each activity window Reduces timing uncertainty More accurate calculation of coupling effects on delay and noise A B Y A B Y One clock cycle

Accurate evaluation of crosstalk effects # paths Negative Time Slack Victim Aggressor Victim Aggressor Min/Max windows overlap: crosstalk delay is estimated Activity windows do not overlap: no crosstalk delay occurs No time windows: pessimistic Min/Max windows: still pessimistic Crosstalk neglected: optimistic Activity windows: accurate

Other signal integrity effects Noise –Crosstalk generates spurious waveforms on supposedly quiet signal lines –May cause unintended flip flop switch –Functional failure Electromigration –High electrical current inside cells –May break vias, contacts wires –The higher the frequency, the higher the damage Analysis is not enough Prevention and repair must be provided

Conventional Signal Integrity Flow Routing change Timing-driven placement Extraction Routing netlistfloorplan Timing o.k.? no yes Noise o.k.? no yes EM o.k.? no yes done Placement change Netlist / floorplan change

Issues with conventional SI flow Trial-and error approach Multiple point tools do separate SI checks –Crosstalk-aware timing –Noise –Signal electromigration (EM) –No common library Check and repair is done in different tools Mutual unawareness of SI effects –Timing repair may cause noise violation –EM repair may cause timing violation Unpredictable number of design iterations

New signal integrity design flow ALF ALF library Timing Noise Electromigration Pre-route optimization Routing Post-route optimization Extraction done netlistfloorplan Initial placement

Accurate timing library Tool results with.lib and ALF compared with SPICE Error criterion Average Std deviation Max - Min.lib % +/- 5.0 % 17.4 % ALF % +/- 2.2 % 11.1 % ALF.lib ALF is more accurate, less pessimistic than.lib

Timing and noise waveforms Timing waveform shaped by aggressor driver resistance Noise waveform shaped by victim driver resistance Accurate characterization of driver resistance is key aggressor victim Timing driving point Timing coupling point Noise waveform Driver resistance ALF

Accurate noise modeling Noise propagation for combinatorial cells Dynamic noise margin for sequential cells Greatly reduces pessimistic noise violations output noise peak input noise peak input pulse width output load cap input pulse width dynamic noise margin output load cap static noise margin ALF

Conditions for EM damage inside cell represented by abstract vector Each vector has associated max. frequency Signal Electromigration A B Y ALF AB Y 1: (10 A) 2: (01 A) 3: (01 Y) 4: (10 A -> 10 Y) 5: (01 B -> 10 Y)

Signal Electromigration Flow ALF library contains max frequency = f(slew, load) for each EM characterization vector in cell Global activity file (GAF) contains actual switching frequency for each design instance vector GAF is generated by event-driven or probabilistic simulation EM violation, if max frequency < actual frequency For optimization, EM frequency limit is transformed into max cap. limit = f(slew) for given frequency After net list change, actual frequency is locally propagated through inserted buffers (ECO GAF)

Design result Design step Automatic floor plan Total P&R Total Extraction Total Optimization Runtime 2 H 20 H 16 H 24 H Design data Cell instances Worst time slack # timing violations # SI violations initial 448K ns final 467K 0.0 ns nm 333MHz, 167MHz et al 8.5mm*8.5mm M Technology Clock frequency Die size Hard macros Total gate count

Conclusion ALF provides comprehensive signal integrity support –Timing, noise, electromigration ALF enables better crosstalk-aware STA –Accurate ALF timing models eliminate the need for proprietary delay calculators ALF enables efficient signal integrity flow for ASIC and SoC designs –Iteration-free analysis and optimization –Sign-off quality ALF is the library for next-generation tools