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ETE 204 - Digital Electronics Counters [Lecture:14] Instructor: Sajib Roy Lecturer, ETE, ULAB

Counters - has n Flip-Flops - can cycle through at most 2n states. ● A counter is a sequential circuit (aka. finite state machine) that cycles through a fixed sequence of states. ● The state of the counter is stored in Flip-Flops. ● An n-bit counter - has n Flip-Flops - can cycle through at most 2n states. Summer 2012 ETE 204 - Digital Electronics 2

Counters 2-bit Counter 3-bit Counter 111 000 001 00 11 01 110 010 10 101 100 011 2-bit Counter 3-bit Counter Summer 2012 ETE 204 - Digital Electronics 3

Counters 2-bit Counter 3-bit Counter using only 3 states 000 00 01 110 010 10 101 011 2-bit Counter using only 3 states 3-bit Counter using only 5 states Summer 2012 ETE 204 - Digital Electronics 4

Binary Counters 3-bit Binary Counter Cycles through all 8 states ● An n-bit binary counter is a counter that cycles through all 2n states in ascending (or descending) order. 111 000 001 3-bit Binary Counter 110 010 Cycles through all 8 states in ascending order 101 100 011 Summer 2012 ETE 204 - Digital Electronics 5

Binary Counters: Design 1.Draw a state graph that specifies the desired sequence of the counter. 2.Construct a state table from the state graph.  One Flip-Flop for each bit in the state. 3.Derive a K-map from the state table for each Flip-Flop input.  Select the type of Flip-Flop to be used. 4.Determine the input equation(s) for each Flip-Flop. Summer 2012 ETE 204 - Digital Electronics 6

Binary Counters: Design Example: State Table (using D FF) Present State Next State FF Inputs C B A C+ B+ A+ + DC DB DA Characteristic Equation: 0 0 0 0 0 1 1 1 Q+ = D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 Summer 2012 ETE 204 - Digital Electronics

Binary Counters: Design Example: K-maps (for D FF inputs) Summer 2012 ETE 204 - Digital Electronics 8

Binary Counters: Design Example: Circuit Diagram (using D FF) Summer 2012 ETE 204 - Digital Electronics 9

Binary Counters: Design Example: State Table (using T FF) Present State Next State FF Inputs Characteristic Equation: C B A C+ B+ A+ TC TB TA 0 0 0 0 0 1 0 0 1 0 1 0 Q+ = T xor Q 0 1 0 0 1 1 0 1 1 1 0 0 Excitation Table: Q Q + T 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 1 0 1 1 1 0 10 Summer 2012 ETE 204 - Digital Electronics

Binary Counters: Design Example: K-maps (for T FF inputs) Summer 2012 ETE 204 - Digital Electronics 11

Binary Counters: Design Example: Circuit Diagram (using T FF) Summer 2012 ETE 204 - Digital Electronics 12

Binary Up-Down Counters What constraints must be placed on the U and D control signals? Summer 2012 ETE 204 - Digital Electronics 13

Binary Up-Down Counters Summer 2012 ETE 204 - Digital Electronics 14

Loadable Counter with Enable Summer 2012 ETE 204 - Digital Electronics 15

Counters: Design 1.Draw a state graph that specifies the desired sequence of the counter. 2.Construct a state table from the state graph.  One Flip-Flop for each bit in the state. 3.Derive a K-map from the state table for each Flip-Flop input.  Select the type of Flip-Flop to be used. 4.Determine the input equation(s) for each Flip-Flop. Summer 2012 ETE 204 - Digital Electronics 16

Counters: Design Example: Design the following counter using D Flip-Flops. Summer 2012 ETE 204 - Digital Electronics 17

Counters: Design Example: State Table (using D FF) 1 1 x x x 1 1 1 1 1 Present State Next State FF Inputs C B A C+ B+ A+ DC DB DA 1 1 x x x 1 1 1 1 1 1 0 0 1 0 1 1 1 1 x x x Excitation Equation: 1 1 0 1 1 1 x x x 0 1 0 D = Q+ 18 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: K-maps (for D FF inputs) DC DB DA Summer 2012 ETE 204 - Digital Electronics 19

Counters: Design Example: Circuit Diagram (using D FF) Summer 2012 ETE 204 - Digital Electronics 20

Counters: Design Example: Design the following counter using T Flip-Flops. Summer 2012 ETE 204 - Digital Electronics 21

Counters: Design Example: State Table (using T FF) 1 1 x x x 1 1 1 1 1 Present State Next State FF Inputs C B A C+ B+ A+ TC TB TA 1 1 x x x 1 1 1 1 1 1 0 0 1 1 1 Excitation Equation: 1 0 1 x x x 1 1 0 1 1 1 x x x 0 1 0 T = Q xor Q+ 22 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: K-maps (for T FF inputs) 23 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: K-maps (for T FF inputs) We could derive TC , TB , and TA directly from the state table, but it is often more convenient to plot next-state maps showing C+, B+, and A+ as functions of C, B, and A, and then derive TC , TB , and TA from these maps. 24 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: Circuit Diagram (using T FF) 25 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: Next States (for T FF inputs) Although the original state table for the counter is not completely specified, the next states of states 001, 101, and 110 have been specified in the process of completing the circuit design 101 110 26 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: Design the following counter using JK Flip-Flops. 27 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: Using JK Flip-Flops Excitation Table: Q Q+ J x 1 1 x 1 x 1 1 1 x 28 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: State Table (using JK FF) 1 1 x x x 1 1 1 1 Present State Next State FF Inputs C B A C+ B+ A+ JC KC JB KB JA KA 1 1 x x x 1 1 1 1 1 1 1 1 1 1 1 x x x 1 1 x x x 1 1 1 0 1 0 29 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: K-maps (for JK FF inputs) 30 Summer 2012 ETE 204 - Digital Electronics

Counters: Design Example: Circuit Diagram (using JK FF) 31 Summer 2012 ETE 204 - Digital Electronics

Questions? 32 Summer 2012 ETE 204 - Digital Electronics