1 EENG 2710 Project Synchronous Counters

2 Counters Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations.

3 Synchronous Counters A counter whose flip-flops are all clocked by the same source and change state in synchronization. The memory section keeps track of the present state. The control section directs the counter to the next state using command and status lines. Present state Directs to next state

4 Counter Terminology A Counter is a digital circuit whose outputs progress in a predictable repeating pattern. It advances one state for each clock pulse. State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter. Count Sequence: The specific series of output states through which a counter progresses. Modulus: The number of states a counter sequences through before repeating (mod-n). Counter directions: –DOWN - count high to low (MSB to LSB) –UP - count low to high (LSB to MSB).

5 Counter Modulus Modulus of a counter is the number of states through which a counter progresses. A Mod-12 UP Counter counts 12 states from 0000 to 1011 (0 to 11 decimal). The process then repeats. A Mod-12 DOWN counter counts from 1011 (to 0000 (11 to 0 decimal), then repeats.

6 State Diagram A diagram that shows the progressive states of a sequential circuit. The progression from one state to the next state is shown by an arrow. – (0000  0001  0010). Each state progression is caused by a pulse on the clock to the sequential circuit.

7 MOD 12 Counter State Diagram With each clock pulse the counter progresses by one state from its present position on the state diagram to the next state in the sequence. This close system of counting and adding is known as modulo arithmetic.

8 Full-sequence Counter An n-bit counter that counts the maximum modulus (2 n ) is called a full-sequence counter such as Mod 2, Mod 4, Mod 8, etc. A 4-bit mod 16 UP counter that counts up from 0000 to 1111 is an example of a full-sequence counter.

9 Counter Timing Diagram (Mod-16 Full-sequence Counter) Shows the timing relationships between the input clock and the outputs Q 3, Q 2, Q 1, …Q n of a counter. For a 4-bit mod 16 counter, the output Q 0 changes for every clock pulse, Q 1 changes on every two clock pulses, Q 2 on four, and Q 3 on 8 clocks. The outputs (Q 0  Q 3 ) of the counter can be used as frequency dividers with Q 0 = clock  2, Q 1 = clock  4, Q 2 = clock  8, and Q 3 = clock  16.

10 Truncated Counter An n-bit counter whose modulus is less than the maximum possible is called a truncated sequence counter, such as mod 3 (n = 2), mod 12 (n = 4). A 4-bit mod 12 UP counter that counts from 0000 to 1011 is an example of a truncated counter

11 Counter Timing Diagram (Mod-12 Truncated Counter The outputs (Q 0  Q 3 ) of the counter can be used as frequency dividers with Q 0 = clock  2, Q 1 = clock  4, Q 2 = clock  12, and Q 3 = clock  12.

12 Designing a Synchronous Up Counter 1.Define the problem. The circuit must count in binary sequence from 0000 to Draw a state diagram

13 Step 3 Designing a JK Flip-Flop Synchronous Up Counter JK Flip-Flop Excitation Table State Table

14 Designing a Synchronous Counter Simplify the Boolean expression for each input

15 MOD-12 Synchronous Counter

Project Assignment Each team will do the following: 1.The team leader will chose a Mod-n JK Flip-Flop Synchronous Up Counter at random form a group of Mod-n JK Flip-Flop Synchronous Up Counter provided by the instructor. 2.Construct a state table. 3.Simplify the Boolean expression for each input using K-maps. 4.Use the simplified J and K expressions to design the Mod-n JK Flip-Flop Synchronous Up Counter. 5.Draw a Schematic Capture Diagram using Xilinx. 6.Simulate the Schematic Capture Diagram using Xilinx. 7.Write a project report in-accordance-with the IEEE format provided by the instructor. 8. Prepare and give a power point presentation. 9.Provide the instructor a paper and electronic (disc copy) of project report and presentation. 16