Design and Synthesis of Universal Asynchronous Receiver and Transmitter (UART) Using Verilog HDL Prepared by: Engr. Qazi Zia, Assistant Professor EED,

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Design and Synthesis of Universal Asynchronous Receiver and Transmitter (UART) Using Verilog HDL Prepared by: Engr. Qazi Zia, Assistant Professor EED, COMSATS Attock1

What is UART  A serializer and de-serializer  An interface between a serial data channel and a machine that works on parallel data format.  There are different types of UARTs having different architectures, coding schemes and clocking schemes.  The simplest UART is a computer MODEM Prepared by: Engr. Qazi Zia, Assistant Professor EED, COMSATS Attock2

MODEM  MODEM has the capability to convert Parallel data into Serial and Serial into Parallel.  A MODEM on transmitting side is controlled by the host machine’s clock and on other side the receiving MODEM is clocked by it’s host machine, so both are asynchronous.  MODEM represents text data in American Standard Code for Information Interchange (ASCII).  In ASCII format each alphabet is encoded by 7 bits augmented by parity bit.  The parity bit is use for error detection.  A start bit at LSB and a stop bit at MSB is concatenated with the 8 bit (7 bit data plus a parity bit) words for transmission. Prepared by: Engr. Qazi Zia, Assistant Professor EED, COMSATS Attock3

Operation  A host processor fetches a data word in parallel format and directs the UART transmitter to transmit this data in serial format.  The UART receiver detects the transmission, receives the data in serial format, removes the start and stop bits and stores the data in parallel format into it’s host machine. Prepared by: Engr. Qazi Zia, Assistant Professor EED, COMSATS Attock4

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