Interrupts, Thermistors, Opto-isolators and Phototransistors Fall 2009 Kipp Schoenwald Stephen Hunte Joseph Storey

Outline Interrupts ◦Vectors and Vector Table ◦Flow Chart ◦Applications  Example 1  Example 2 Thermistors ◦Theory ◦Applications Opto-isolators ◦Theory ◦Applications Phototransistors ◦Theory ◦Applications

Interrupts Q: What are interrupts good for? A: Interrupts provide a means to temporarily suspending current instruction for more important tasks. Q: How are interrupts initiated? A: Interrupts are initiated by one of the following: Hardware interrupts ◦Peripherals such as a printer or fax machine ◦Computer Operator via keyboard, mouse or power on reset button ◦Another computer Software interrupts ◦Timer resets ◦Timer interrupts ◦Traps ◦Request for input or output ◦Arithmetic overflow error Q: What is the alternative to interrupt and how does it work? A: Polling – Polling is an loop that continuously looks at all of the inputs.

Interrupts EXAMPLES: 1. Problem: Power Fails (someone kicks the power cord out of your laptop) Solution: R/C circuit senses impending power loss and runs an interrupt routine that can select the battery as the power supply 2. Problem: Car engine overheats Solution: Thermal couple senses temperature. Runs a interrupt routine that turns on warning light

Interrupts: Vectors Definitions: 1. Interrupt Service Routine (interrupt handler): This is a “more important” instruction code that interrupts your main program code. The routine is specific to the type of interrupt called. 2. Interrupt Vector: This is an address in memory where the ISR instruction code is located. It is the starting address of the code. (Like a pointer) 3. Interrupt Vector Table: This is a table indicating the interrupt vector

Interrupts: Vector Table The interrupt vector table is located: ◦Pg 61 of Reference Manual (thick book) ◦Pg 56 of Device User Guide (medium thick book) ◦Pg 2 of the Reference Guide (thin book).

Interrupts: MON12 Vector Table MON12 interrupt vectors are used. ($0F00-$0FFF ) The microcontroller calls ISR’s specified in the $FFxx range. MON12’s calls ISR’s specified by the user in the $0Fxx range

Interrupts: MON12 Vector Table The MON12 Interrupt Table shows both the actual Vector Table addresses, and the Ram Vector Table addresses

Interrupts: Flow Back to Main Program Back to Main Program X X I I Software Interrupt (SWI) Maskable Wait For Interrupt (WAI) Mask Set Hardware Interrupt Begin Interrupt Program (ISR) Begin Interrupt Program (ISR) Store MPU Registers to SP Condition Code Register Accumulator B Accumulator A Index Register (MS) Index Register (LS) Program Counter (MS) Program Counter (LS) SP SP -1 SP -2 SP -3 SP -4 SP -5 SP -6 Condition Code Register Stack Pointer Load Interrupt Vector into PC Complete Current Instruction Complete Current Instruction Complete Current Instruction Complete Current Instruction 0 1YES NO Set Mask (CCR4) (set to 1) Interrupt Vector Clear Mask (CCR4) (set to 0) Maskable Wait For Interrupt (WAI) Hardware Interrupt Mask Set NO YES 01 NO Important Slide Important Slide

Interrupts: Flow: IRQ Example 1 1. If I bit in CCR is not set (I=0) and IRQ goes low for at least φ2 cycle, the IRQ sequence is entered. 2. Internal registers  stored to RAM (SP). 3. The IRQ mask bit set (I=1). 4. Data at FFF2 gets loaded into PCH 5. Data at FFF3 gets loaded into PCL 6. PC contents go out on address bus during φ1. 7. Contents of the location addressed enter instruction register and are decoded as first instruction of interrupt routine. 8. If it is a more than 1-byte instruction, additional bytes enter MPU for execution. If not, go to next step 9. After execution, step 7 is repeated for subsequent instructions. This is repeated until “RTI” is executed. RTI tells the MPU that service is complete and that it may reload the registers and continue the main program from where it left off. Back to Main Program Back to Main Program Software Interrupt (SWI) Maskable Wait For Interrupt (WAI) Mask Set Hardware Interrupt Begin Interrupt Program (ISR) Begin Interrupt Program (ISR) Store MPU Registers to SP Load Interrupt Vector into PC Complete Current Instruction Complete Current Instruction Complete Current Instruction Complete Current Instruction 0 1YES NO Set Mask (CCR4) (set to 1) Clear Mask (CCR4) (set to 0) Maskable Wait For Interrupt (WAI) Hardware Interrupt Mask Set NO YES 01 NO

Interrupts: Applications: Example 2 Write a routine to interrupt the MCU after 5ms of elapsed time, assuming prescaler is 1. Use output compare (OC) five. TFLG1EQU$004E/*OC5 flag*/ TIEEQU$004C/*OC5 enable*/ TCTL1EQU$0048/*OC5 condition*/ SECONDADEQU$FFE4/*OC reference location*/ TCNTEQU$0044/*counter*/ TC5EQU$005A/*OC5*/ TIOS EQU $0040/*timer input capture or output compare select*/ ORG$1000 /*begin routine at a chosen address*/ SEI /*set the I bit of the condition code register*/ LDAA% STAATIOS/*configures port 5 as output compare (default is 0)*/ STAATFLG1 /*clear previously set OC5 flag*/ STAATIE /*enable OC5 Interrupt*/ configure ports as input or output LDAB% STABTCTL1 /*OC condition: PA5 = high (for a successful compare)*/ LDX#$2000 /*$2000 is the address where you chose to put your ISR*/ STXSECONDAD /*stores this address “pointer” to the address that OC refers to. High byte (20)  $FFE4, and Low byte (00)  FFE5*/ LDDTCNT /*Loads current value of counter*/ ADDD#$9C40 /*adds 40,000cycles (5ms) to the current time (this equals the time when the ISR is to be run)*/ STDTC5 /*stores this value to be compared*/ CLI /*clear the I bit of the condition code register*/ Important Slide Important Slide

Outline Interrupts ◦Vectors and Vector Table ◦Flow Chart ◦Applications  Example 1  Example 2 ◦Priorities ◦Interrupt Stack Thermistors ◦Theory ◦Applications Opto-isolators ◦Theory ◦Applications Phototransistors ◦Theory ◦Applications

Interrupts: Stack The Stack Pointer Register holds the location of the top of the stack at all times. When the CPU detects an interrupt the contents of the register are pushed on the stack. After completion of the interrupt the saved registers are retrieved from the stack. The first register pushed onto the stack will be the last register pulled from the stack.

CCR ACC B ACC A X HI X LO Y HI Y LO RTN HI RTN LO RTN – address of next instruction in Main Program, upon return from interrupt. X LO and Y LO are the low bytes of X and Y registers. X HI and Y HI are the high bytes of X and Y registers. ACC A and ACC B are the accumulators. CCR is the Code Condition Register Interrupts: Stack

CCR ACC B ACC A X HI X LO Y HI Y LO RTN HI RTN LO First Pushed In Last Pulled Off Last Pushed In First Pulled Off Higher Address Lower Address Stack Pointer before Interrupt Stack Pointer after Interrupt

Interrupts: Priorities Interrupt Types Presents

Interrupts: Priorities Non-Maskable Interrupts 6 Non-Maskable Interrupts Always interrupts program execution Priority over Maskable Interrupts. Not subject to global masking Sets the X and I bit of the CCR when serviced

Interrupts: Priorities Non-Maskable Interrupts Priority of Non-Maskable Interrupts 1.POR of RESET pin 2.Clock monitor reset 3.COP watchdog reset 4.XIRQ interrupt 5.Unimplemented instruction trap 6.Software interrupt (SWI)

Interrupts: Priorities Reset Forces MCU to: ◦Assume set of initial conditions ◦Begin executing instructions at an assigned starting address Like interrupts, resets have a vector to define the starting address of code to be run Unlike interrupts, they do not return to original code location Resets have different vectors to allow execution of individualized code

Interrupts: Priorities When a reset is triggered: The address from the vector is loaded into the program counter S, X, and I bits are set in the CCR MCU hardware is initialized to reset state Check for any interrupts that have occurred

Interrupts: Priorities Clock Monitor Reset Protects against clock failure Set by CME control bit If enabled, system resets if no clock edges are detected within a set period. Computer operating Properly (COP) Reset Protects against software failures (infinite loops, etc) When enabled (NOCOP bit in CONFIG register), resets if free-running watchdog timer rolls over $FFFF Timer rate is set in the OPTION register. System E- clock is divided by 2 15 and further scaled by 1, 2, or 4

Interrupts: Priorities XIRQ Externally triggered PE0 pin low = XIRQ interrupt Sets X and I bits RTI returns the X and I bits to original states prior to execution

Interrupts: Priorities Opcode Trap and SWI Very low priority Any enabled interrupt source pending prior to the initialization of Trap or SWI will take precedence. Once process has begun neither can be interrupted.

Interrupts: Priorities Maskable Interrupts 27 Maskable Interrupts Sets I bit in CCR when serviced Automatically cleared by RTI interrupt Follows default priority, but any one Maskable Interrupt can be elevated using HIPRO (Higher Priority)

Interrupts: Priorities Maskable Interrupts Priority of Maskable Interrupts 1.IRQ 2.Real-Time Interrupt 3.Standard Timer Channel 0 4.Standard Timer Channel 1 5.Standard Timer Channel 2 6.Standard Timer Channel 3 7.Standard Timer Channel 4 8.Standard Timer Channel 5 9.Standard Timer Channel 6 10.Standard Timer Channel 7 11.Standard Timer Overflow 12.Pulse Accumulator A Overflow 13.Pulse Accumulator Input Edge 14.SPI transfer Complete 15.SCI system 16.ATD 17.Port J 18.CRG PLL Lock 19.CRG Self Clock Mode 20.Flash 21.CAN Wakeup 22.CAN Errors 23.CAN Receive 24.CAN Transmit 25.Port P 26.PWM Emergency Shutdown 27.VREG LVI Discusse d in Timer Lecture

Interrupts: Priorities IRQ Only external maskable interrupt signal IRQE bit on IRQCR Register ◦IRQE=1: Falling Edge Sensitive ◦IRQE=0: Low Level-Sensitive Peripheral Subsystems (all other Maskable Interrupts) Flag bit and interrupt enable bit ATD, Timers, PWM, serial communications, etc.

Interrupts: Priorities Highest Priority Interrupt (HPRIO) HPRIO register moves one maskable interrupt to top of priority list Cannot change priority of non- maskable interrupts Procedure to increase priority of maskable interrupt: ◦Set I bit to disable maskable interrupts ◦Write low byte of interrupt vector to HPRIO ◦Clear I bit to re-enable maskable interrupts

Address: $001F Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit PSEL7PSEL6PSEL5PSEL4PSEL3PSEL2PSEL1- PSEL[7:1] – Priority Select Bits (HPRIO) ◦Selects one interrupts source to be elevated ◦Can only be written while I-bit in the CCR is set and maskable interrupts turned off ◦Write the low byte of the maskable interrupt vector to HPRIO to elevate that maskable interrupt to the highest priority ◦Ex: writing $DE to HPRIO elevates the Standard Timer Overflow to highest priority (Standard Timer Overflow vector = $FFDE) Interrupts: Priorities

Outline Interrupts ◦Vectors and Vector Table ◦Flow Chart ◦Applications  Example 1  Example 2 ◦Priorities ◦Interrupt Stack Thermistors ◦Theory ◦Applications Opto-isolators ◦Theory ◦Applications Phototransistors ◦Theory ◦Applications

Thermistor Thermistor - Temperature sensitive resistor Their change in electrical resistance is very large and precise when subjected to a change in temperature. Thermistors exhibit larger parameter change with temperature than thermocouples and RTD’s. Thermistor - sensitive Thermocouple - versatile RTD – stable Generally composed of semiconductor materials. Very fragile and are susceptible to permanent decalibration.

Thermistor Probe One of many available probe assemblies TEFLON INSULATION TEFLON TUBE 2” MIN..095” DIA. MAX..11 DIA. MAX. #32 TINNED COPPER WIRE 3” LONG

Thermistor Characteristics Most thermistors have a negative temperature coefficient (NTC); that is, their resistance decreases with increasing temperature. Positive temperature coefficient (PTC) thermistors also exist with directly proportional R vs. T. Extremely non-linear devices (high sensitivity) Common temperature ranges are –100 oF (~-75 oC) to +300 oF (~150 oC) Some can reach up to 600 oF

An individual thermistor curve can be very closely approximated by using the Steinhart- Hart equation: = T = Degrees Kelvin R = Resistance of the thermistor A,B,C = Curve-fitting constants Typical Graph Thermistor (sensitive) RTD (stable) Thermocouple (versatile) T V or R Thermistor R-T Curve

Temperature Measurement “Wheatstone bridge” with selector switch to measure temperature at several locations Thermistor Applications

Resistor is set to a desired temperature (bridge unbalance occurs) Unbalance is fed into an amplifier, which actuates a relay to provide a source of heat or cold. When the thermistor senses the desired temperature, the bridge is balanced, opening the relay and turning off the heat or cold. Temperature Control high gain amplifier relay thermistor variable resistor for setting desired temperature Thermistor Applications

Operation similar to traditional transistors Have a collector, emitter, and base Phototransistor base is a light-sensitive collector-base junction Small collector to emitter leakage current when transistor is switched off, called collector dark current Phototransistor Background

Phototransistor Package Types

Phototransistor Construction

A light sensitive collector base p-n junction controls current flow between the emitter and collector As light intensity increases, resistance decreases, creating more emitter-base current The small base current controls the larger emitter-collector current Collector current depends on the light intensity and the DC current gain of the phototransistor. Phototransistor Operation

The phototransistor must be properly biased Basic Phototranstor Circuit

Obstacle Avoidance Example

Adjust baffle length to obtain a specific detection range Use infrared components that won’t be affected by visible light Use ~ 220 ohm resistors for LED’s Use multiple sensors in a row to detect narrow obstacles Phtotransistor Summary

They must be properly biased They are sensitive to temperature changes They must be protected against moisture Hermetic packages are more tolerant of severe environments than plastic ones Plastic packages are less expensive than hermetic packages Phtotransistor SUmmary

Optoisolator Background Operation similar to relays Used to control high voltage devices Excellent noise isolation because switching circuits are electrically isolated Coupling of two systems with transmission of photons eliminates the need for a common ground Optoisolator Background

Glass dielectric sandwich separates input from output Optoisolator Construction

Input Stage = infrared emitting diode (IRED) Output Stage = silicon NPN phototransistor Optoisolator Schematic

Contact Info Kipp Schoenwald Stephen Hunte Joseph 1.Wikipedia.org 2.Bishop R., Basic Microprocessors and the 6800