DDR Evolution and Memory Market Trends Bill Gervasi Technology Analyst

2 Topics to Cover The SDRAM Roadmap The SDRAM Roadmap DDR-I & DDR-II Comparison DDR-I & DDR-II Comparison Why DDR-I 400 is Boutique Why DDR-I 400 is Boutique Memory Modules Changes Memory Modules Changes

3 DRAM Evolution Simple, incremental steps “DDR I” “DDR II” 1100MB/s PC133 DDR MB/s DDR MB/s DDR MB/s 1600MB/s DDR200 “SDR” DDR MB/s DDR400? 3200MB/s Mainstream Memories DDR MB/s Is DDR-I 400 a temporary blip?

4 Key to System Evolution Never over-design! Never over-design! Implement just enough new features to achieve incremental improvements Implement just enough new features to achieve incremental improvements Use low cost high volume infrastructure Use low cost high volume infrastructure  Processes  Packages  Printed circuit boards

5 Posed To Me at Platform & JEDEX Why will DDR-I at 400 MHz data rate be a “boutique” solution? Why will DDR-II at 400 MHz data rate be a “mainstream” solution? The answer is to look at what new is going into DDR-II

6 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination

7 The DDR II Family DDR II similarities to DDR I: DDR II similarities to DDR I:  Compatible RAS/CAS command set & protocol DDR II differences from DDR I: DDR II differences from DDR I:  DDR I = 2.5V, DDR II = 1.8V  Prefetch 4  Differential data strobes  Improved command bus utilization:  Write latency as a function of read latency  Additive latency to help fill holes  New FBGA package & memory modules  Tighter package parasitics

8 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination Lower Voltage

9 1.8V Signaling 2.5V DDR-II (SSTL_18) 1.60V 0.90V 1.43V 1.07V 1.25V 0V 0.90V 1.03V 0.77V 0.65V 1.15V 1.8V VSS VDDQ VREF VIHac VIHdc VILdc VILac VREF VSS VDDQ VIHac VIHdc VILdc VILac DDR-I (SSTL_2)

10 I/O Voltage Impact on Timing Signal integrity is a serious challenge at high data rates!!! (duh!) Signal integrity is a serious challenge at high data rates!!! (duh!) Assume 1mV/ps edge slew rate Assume 1mV/ps edge slew rate  DDR-I = 700 mV (V IL  V IH ) = 700 ps  DDR-II = 500 mV (V IL  V IH ) = 500 ps Helps meet the need for speed Helps meet the need for speed

11 1.8V Signaling = Major Power Savings 3.3V 1.8V 2.5V

12 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination Prefetch 4

13Prefetch Today’s SDRAM architectures assume an inexpensive DRAM core timing Today’s SDRAM architectures assume an inexpensive DRAM core timing DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O

14 Prefetch 2 Versus 4 CK READ Prefetch 2 Prefetch 4 Core access time Costs $$$ Essentially free data

15 Prefetch Impact on Cost By doubling the prefetch depth, cycle time for column reads & writes relaxed, improving DRAM yields DDR-I DDR-II Pre- fetch ns 6 ns 5 ns 6 ns 7.5 ns 10 ns DDR Family Data Rate Cycle Time Starts to get REAL EXPENSIVE! Comparable to DDR266 in cost

16 DDR-I 400 Prefetch DDR-I prefetch of 2 means expensive core timing DDR-I prefetch of 2 means expensive core timing Lower yields Lower yields Conclusion: DDR-I 400 will maintain a price premium for a long while Conclusion: DDR-I 400 will maintain a price premium for a long while

17 Why Not Prefetch = 8? DIMM width = 64 bits DIMM width = 64 bits PCs use 64b, servers use 128b (2 DIMMs) PCs use 64b, servers use 128b (2 DIMMs)  64 byte prefetch okay for PC, but…  128 byte prefetch for servers wastes bandwidth DDR-II must service all applications well to insure maximum volume  minimum cost DDR-II must service all applications well to insure maximum volume  minimum cost

18 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination Differential Strobe

19 Differential Data Strobe Just as DDR added differential clock to SDR Just as DDR added differential clock to SDR DDR II adds differential data strobe to DDR I DDR II adds differential data strobe to DDR I Transition at the crosspoint of DQS and DQS Transition at the crosspoint of DQS and DQS Route these signals as a differential pair Route these signals as a differential pair  Common mode noise rejection  Matched flight times

20 Differential Data Strobe DQS high time V REF DQS low time DQS DQS high time V REF DQS low time DQS Normal balanced signal Mismatched Rise & Fall signal Error!

21 Differential Data Strobe DQS high time V REF DQS low time DQS DQS high time V REF DQS low time DQS Normal balanced signal Mismatched Rise & Fall signal DQS Significantly reduced symmetry error

22 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination Command Bus

23 Additive Latency Command slot availability is disrupted by CAS latency even on seamless read bursts Command slot availability is disrupted by CAS latency even on seamless read bursts  Sometimes with odd CAS latencies, sometimes with even  These collisions can be avoided by shifting READs and WRITEs in the command stream Additive latency shifts R & W commands earlier – applies to both Additive latency shifts R & W commands earlier – applies to both

24 Read Latency In the past, data access from a READ command was simply CAS Latency In the past, data access from a READ command was simply CAS Latency Combined with Additive Latency, ability to order commands better Combined with Additive Latency, ability to order commands better

25 Read & Additive Latencies CK ACTRD CK ACTRD CAS Latency RL = AL + CL Additive Latency data

26 Write Latency Complex controllers had collisions between command slots and data bus availability Complex controllers had collisions between command slots and data bus availability These are eliminated in DDR II by setting Write Latency = Read Latency – 1 These are eliminated in DDR II by setting Write Latency = Read Latency – 1 Combined with Additive Latency, lots of flexibility in ordering commands Combined with Additive Latency, lots of flexibility in ordering commands

27 Write & Additive Latencies CK ACTWR CK ACTWR WL = RL – 1 CL – 1 WL = AL + CL – 1 = RL – 1 Additive Latency Additive Latency = 0 data

28 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination FBGA Package

29 Managing Power (and its relationship to packaging)

30 Power = CV 2 f%# Factors: Capacitance (C) Capacitance (C) Voltage (V) Voltage (V) Frequency (f) Frequency (f) Duty cycle (%) Duty cycle (%) Power states (# circuits in use) Power states (# circuits in use) Keys to low power design: Reduce C and V Match f to demand Minimize duty cycle Utilize power states

31 Package Capacitance (pF) Reduced capacitance lowers power, makes design easier Reduced capacitance lowers power, makes design easier Input Capacitance Input/Output Capacitance MinMaxDelta Input Capacitance Input/Output Capacitance TSOP-II Package FBGA Package Approximate 10-25% reduction

32 From DDR-I to DDR-II Lower Voltage Prefetch 4 Differential Strobe Command Bus FBGA Package On-Die Termination

33 On-Die Termination Reduces system cost while improving signal integrity Data Controller V TT = V DD Q  2 DRAM Data Controller DRAM VDDQ  2 DDR-I DDR-II

34 DDR-I 400 Issues DDR-I 400 systems are hard to design robustly DDR-I 400 systems are hard to design robustly No vendor interoperability guarantees No vendor interoperability guarantees DDR-II offers other performance benefits besides peak data rate DDR-II offers other performance benefits besides peak data rate DDR-I 400 runs hot DDR-I 400 runs hot Exists because DDR-II is late Exists because DDR-II is late

35 DDR-I 400 Conclusion The JEDEC roadmap represents the industry focus for mainstream products The JEDEC roadmap represents the industry focus for mainstream products  DDR-I tops out at 333 MHz data rate  DDR-II starts at 400 MHz data rate This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume It DOES mean that there will be price premiums for this speed bin It DOES mean that there will be price premiums for this speed bin

36Modules

37Modules DDR-I DDR-I  Unbuffered DIMM  Registered DIMM  SO-DIMM  Micro-DIMM New: New:  32b-DIMM DDR-II DDR-II  Unbuffered DIMM  Registered DIMM  SO-DIMM  Micro-DIMM New: New:  Mini-DIMM

38 Unbuffered & Registered DIMMs Same physical size: 133 mm (5.25”) Same physical size: 133 mm (5.25”) New socket; more pins, tighter pitch New socket; more pins, tighter pitch “Same plane referencing” pinout “Same plane referencing” pinout Target markets unchanged Target markets unchanged  Servers  Workstations  Full form factor desktop PC

39SO-DIMM Same size as before: 67.6 x mm Same size as before: 67.6 x mm Same 200 pin socket as before Same 200 pin socket as before  Uses 1.8V key position No longer supports x72 (ECC) or registered No longer supports x72 (ECC) or registered Target markets change: Target markets change:  DDR-I: Mobile, blade server  DDR-II: Does not support blade server, small form factor PC possible

40Mini-DIMM New to DDR-II… no DDR-I equivalent New to DDR-II… no DDR-I equivalent Supports x72 (ECC) and registered Supports x72 (ECC) and registered Larger than SO-DIMM: 82 mm Larger than SO-DIMM: 82 mm New socket required New socket required Target market: blade server Target market: blade server Intent is to support stacking Intent is to support stacking  If anyone figures out how to stack BGA

41Micro-DIMM Same footprint: 45.5 x 30-ish mm Same footprint: 45.5 x 30-ish mm New connector New connector  High pin count mezzanine connector  Two part: one on mobo, one on module  0.4 mm pitch

4232b-DIMM New to DDR-I… no DDR-II version yet New to DDR-I… no DDR-II version yet X32 only X32 only Ultra low cost Ultra low cost New connector New connector Target market: peripherals, e.g. printers Target market: peripherals, e.g. printers

43 What Can Change?

44 Small Form Factor PC PC memory usage flattened out PC memory usage flattened out SO-DIMM or Mini-DIMM meet the needs of most PCs SO-DIMM or Mini-DIMM meet the needs of most PCs DIMM could yield to smaller module for most desktop PCs DIMM could yield to smaller module for most desktop PCs Saves ~10,000 mm 2 board space Saves ~10,000 mm 2 board space

45

46 North Bridge Copper Slots FlexATX Footprint With DIMM: 17k mm 2 With SO-DIMM: 7k mm 2 Area saved ~ 60%

47Mobile DDR-I SO-DIMM had 2X capacity of Micro-DIMM (assuming TSOP) DDR-I SO-DIMM had 2X capacity of Micro-DIMM (assuming TSOP) DDR-II Micro-DIMM has same capacity as SO-DIMM DDR-II Micro-DIMM has same capacity as SO-DIMM Differences: Differences:  SO-DIMM supports 1 st generation die  Micro-DIMM connector change scary However, possible that the Micro- DIMM displaces the SO-DIMM for all mobile market However, possible that the Micro- DIMM displaces the SO-DIMM for all mobile market

48 Small Module Capacity

49Summary DDR-II offers many incremental improvements over DDR-I DDR-II offers many incremental improvements over DDR-I  Lower voltage, higher prefetch, differential strobes, more efficient command bus, higher quality package, on-die termination DDR-I 400 likely to stay a profitable niche DDR-I 400 likely to stay a profitable niche New module configurations may impact markets – watch for growth of Micro- DIMM, possible shrink of SO-DIMM in DDR-II generation New module configurations may impact markets – watch for growth of Micro- DIMM, possible shrink of SO-DIMM in DDR-II generation

50 Thank You