Clock Generation Module MTT CLOCK GENERATION MODULE (CGM)

Clock Generation Module MTT Clock Generation Module 68HC08 CPU System Integration Module (SIM) Clock Generation Module (CGM) Timer Interface Module (TIM) Direct Memory Access Module (DMA) Serial Communications Interface (SCI) Internal Bus (IBUS) Serial Peripheral Interface (SPI) Random Access Memory (RAM) Electronically Programmable ROM LVI COP Monitor ROM IRQ BREAK RESET Generates base clock frequency for MPU Two selectable clock sources Crystal Oscillator Phase Lock Loop (PLL) –Uses Crystal Oscillator to produce faster clock rate Output used by System Integration All sub systems use the system clock for timing –Except Serial Communications Module Uses Crystal Oscillator frequency

Clock Generation Module MTT CGM Block Diagram BCS PHASE DETECTOR LOOP FILTER FREQUENCY DIVIDER VOLTAGE CONTROLLED OSCILLATOR BANDWIDTH CONTROL LOCK DETECTOR CLOCK CGMXCLK CGMOUT CGMVDVCGMVCLK SIMOSCEN CRYSTAL OSCILLATOR INTERRUPT CONTROL CGMINT CGMRDV PLL ANALOG  CGMRCLK SELECT CIRCUIT LOCKAUTOACQ VRS[7:4] PLLIEPLLF MUL[7:4] CGMXFCV SS V DDA OSC1 OSC2 TO SIM, SCI TO SIM PTC3 MONITOR MODE A B S* USER MODE *When S = 1, CGMOUT = B

Clock Generation Module MTT Crystal Oscillator External crystal is connected between OSC1 and OSC2 CGMXCLK is oscillator clock output Equal to external crystal frequency 4 x internal bus frequency (if selected) WHEN VCO IS USED TO GENERATE SYSCLK, THE CRYSTAL IS: Buffered to produce CGMRCLK –Reference frequency for PLL circuit SIM module can enable/disable oscillator via SIMOSCEN line Stops crystal oscillator and PLL module

Clock Generation Module MTT Phase Lock Loop Module PLL consists of Bandwidth programmable Voltage Controlled Oscillator (VCO) Modulo programmable VCO frequency divider Phase detector Loop filter Lock Detector Operate in Acquisition Mode or Tracking Mode CGMVCLK is PLL module output Exact integral multiple of CGMXCLK 4 x internal bus frequency (if selected)

Clock Generation Module MTT Programmable VCO Generates CGMVCLK based on Frequency divider –Divides frequency producing faster clock –Multiplier select bits control frequency division Phase detector –Compares CGMXCLK and output of Frequency divider –Detects phase error –Generates correction pulse Loop filter –Translates phase detector correction pulse into voltage correction for VCO Programmable bandwidth to improve noisy immunity VCO range bits determine bandwidth limits

Clock Generation Module MTT Sequence for PLL Frequency Calculations Goal: 4MHz bus frequency from a 2 MHz crystal. 1.Select a desired bus frequency, F BUSDES. F BUSDES = 4 MHz 2.Calculate desired VCO frequency(four times the desired bus frequency),F VCLKDES F VCLKDES = 4 x F BUSDES F VCLKDES = 4 x F BUSDES = 4 x 4 MHz = 16 MHz 3.Choose a practical PLL Reference frequency, F RCLK. F RCLK = 2 MHz 4.Select a VCO frequency multiplier, N N = F VCLKDES / F RCLK (nearest positive integer) N = F VCLKDES / F RCLK = 16 MHz / 2 MHz = 8 5.Calculate and verify the adequacy of the VCO and Bus frequencies,F VCLCK and F BUS. F VCLK = N x F RCLK F VCLCK = N x F RCLK = 8 x 2 MHz = 16 MHz F BUS = (F VCLK ) / 4 6.Select a VCO linear range multiplier, L. L = F VCLK / F NOM = 16 MHz / MHz = = 3 L = F VCLK / F NOM (nearest positive integer) where F NOM = nominal VCO frequency = Volts 7.Calculate and verify the VCO programmed center-of-range frequency,F VRS. F VRS = L x F NOM ­ F VCLK F VRS = L x F NOM = 3 x MHz = MHz Was final VCO center frequency F VRS and actual VCO frequency F VCLK within acceptable limits? Acceptable range: 2.5 MHz - 32 MHz For best PLL operation F VRS and F VCLK should be as nearly equal as possible

Clock Generation Module MTT Sequence PLL Frequency Calculations Cont. 8.Verify the choice of N and L by comparing F VCLK to F VRS and F VCLKDES. For proper operation, F VCLK must be within the application’s tolerance of F VCLKDES, and F VRS must be as close as possible to F VCLK. NOTE: *** Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 9.Program the PLL registers accordingly: a.In the upper 4 bits of the PLL programming register (PPG), program the binary equivalent of N. b.In the lower 4 bits off the PLL programming register (PPG), program the binary equivalent of L.

Clock Generation Module MTT PLL Programming PLL Programming Register (PPG) MUL7-MUL4 –VCO frequency divider control bits –Set equal to N value, (1 to 15) –Reset selects F VCLK frequency multiplier of 6 VRS7-VRS4 –VCO range select bits –Set equal to L value, (1 to 15) –Reset selects F VCLK range multiplier of 6 Can not be written while PLL is on READ: WRITE: RESET: MUL7MUL6MUL5MUL4VRS7VRS6VRS5VRS4PPG

Clock Generation Module MTT PLL Enable PLL Control Register (PPG) PLL On (PLLON) –Activates PLL and enables the VCO clock(CGMVLCK) without driving CGMOUT 1 = PLL module on 0 = PLL module off –Can not be cleared when BCS bit set Bus Clock Select (BCS) –Selects CGMOUT source 1 = PLL module = CGMVCLK, VCO Clock 0 = Crystal oscillator = CGMXCLK –Can not be set when PLLON is cleared –CGMOUT frequency is 1/2 the frequency of the selected clock WRITE: READ:PLLF1111 RESET: PLLIEPLLONBCS PCTL

Clock Generation Module MTT PLLON and BCS must be written to separately PLLON = 0, BCS = 0 –Set PLLON first Allows PLL stabilize PLLON = 1, BCS = 1 –Clear BCS first PLLON = 1, BCS = 0 –Can change BCS or PLLON at any time PLLON = 0, BCS = 1 –Invalid setting PLL Enable

Clock Generation Module MTT CGM Exercise PART 1: Calculate frequency values, N, and L to configure the system for an 8 MHz bus clock from a 4 MHz external crystal. PART 2: Write the code sequence to program the CGM registers to achieve the above frequency and enable the proper clock source. Given: * Initialize Clock Generation Module ORG$001C PCTLRMB1 PBWCRMB1 PPGRMB1

Clock Generation Module MTT Additional Information - Acquisition vs Tracking - Acquisition Mode Large frequency corrections required to PLL module Frequency is not locked in Tracking Mode VCO frequency is near programmed frequency, small corrections required Frequency is locked in

Clock Generation Module MTT Additional Information - Auto vs Manual - PLL Bandwidth Control Register (PBWC) AUTO - Automatic Bandwidth Control (Acquisition vs Tracking) 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK - Lock Indicator (Auto bit set only) 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ - Acquisition1 = Tracking mode 0 = Acquisition mode XLD - Crystal Loss Detect 1 = Crystal reference is not active 0 = Crystal reference is active –To check the status of the crystal reference: 1) Write a logic one to XLD 2) Wait N x 4 cycles. (N is the VCO Frequency Multiplier.) 3) Read XLD. PBWC WRITE: READ:LOCK0000 RESET: AUTOACQ XLD

Clock Generation Module MTT Additional Information - Interrupts - PLL Control Register(PCTL) PLL Interrupt Enable (PLLIE) –Enables CPU interrupt when LOCK bit changes –Disabled when in manual mode PLL Interrupt Flag (PLLF) –Becomes set when PLL enters or leaves locked state WRITE: READ:PLLF1111 RESET: PLLIEPLLONBCS PCTL

Clock Generation Module MTT Additional Information - Low Power Modes - Rescue Mode PLL will continue to operate in case of crystal failure Low Power Modes WAIT –Does not affect CGM STOP –Disables CGM by driving SIMOSCEN line low –Disables VCO –Clears BCS bit PLL Bypass Mode (alternative low power) –Clear BCS and PLLON bits Disables PLL Switches to crystal oscillator

Clock Generation Module MTT Register Summary WRITE: READ:PLLF1111 RESET: PLLIEPLLONBCS PCTL WRITE: READ:LOCK0000 RESET: AUTOACQ PBWC READ: WRITE: RESET: MUL7MUL6MUL5MUL4VRS7VRS6VRS5VRS4 PPG XLD

Clock Generation Module MTT EXERCISE SOLUTION - PART 1 - Goal: 8 MHz bus frequency from a 4 MHz crystal. 1.F BUSDES = 8 MHz 2.F VCLKDES = 4 x F BUSDES = 4 x 8 MHz = 32 MHz 3.F RCLK = 4 MHz 4. N = F VCLKDES / F RCLK = 32 MHz / 4 MHz = 8 5.F VCLK = N x F RCLK = 8 x 4 MHz = 32 MHz 6.L = F VCLK / F NOM = 32 MHz / MHz = 6.51 = 7 7.F VRS = L x F NOM = 7 x MHz = 34.4 MHz (out of range) F VRS = L x F NOM = 6 x MHz = 29.5 MHz MUL7-MUL4 = N = 8 VRR7-VRR4 = L = 6

Clock Generation Module MTT EXERCISE SOLUTION - PART 2 - * Initialize Clock Generation Module ORG$001C PCTLRMB1 PBWCRMB1 PPGRMB1 CGMINITMOV#0,PCTL;Turn off PLL, on by default MOV#$86,PPG;Set MUL and VRR bits MOV#$20,PCTL;Turn on PLL MOV#$10,PCTL;Select CGMVCLK(PLL) source