ECE 331 – Digital System Design Power Dissipation and Additional Design Constraints (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

Fall 2010ECE Digital System Design2 Material to be covered … Supplemental Chapter 8: Sections 1 – 5

Fall 2010ECE Digital System Design3 Power Dissipation

Fall 2010ECE Digital System Design4 Power Dissipation Each integrated circuit (IC) dissipates power P T = P S + P D – P T = total power dissipated by IC – P S = static or quiescent power dissipation – P D = dynamic power dissipation

Fall 2010ECE Digital System Design5 Static Power Dissipation P S = V CC * I CC – V CC = supply voltage – I CC = quiescent supply current – P S = static power consumption I CC and V CC are specified in the datasheet for the integrated circuit (IC). For CMOS devices, P S is very small.

Fall 2010ECE Digital System Design6 74LS00 Datasheet

Fall 2010ECE Digital System Design7 Static Power Dissipation Example: 74LS00 (Quad 2-input NAND) – Supply voltage 4.75 V <= VCC <= 5.25 V – Supply current High output: I CCmax = 1.6 mA Low output: I CCmax = 4.4 mA – Maximum static power dissipation High output: P S = 8.4 mW Low output:P S = 23.1 mW

Fall 2010ECE Digital System Design8 Static Power Dissipation – Duty Cycle Clock signal typically has 50% duty cycle – P S = P S_high * t high + P S_low * t low P S_high = 8.4 mW P S_low = 23.1 mW Assume 50% duty cycle (high / low half the time) P S = 8.4 mW * mW * 0.5 = 15.8 mW Assume 60% duty cycle (high 60% of the time) P S = 8.4 mW * mW * 0.4 = mW

Fall 2010ECE Digital System Design9 Dynamic Power Dissipation For TTL devices, P D is negligible compared to P S.  Assume P S = 0 For CMOS devices, P D dominates P T.  P D >> P S P D in CMOS circuits arises from the movement of charge into and out of the device capacitance.

Fall 2010ECE Digital System Design10 Dynamic Power Dissipation In CMOS devices, charge is stored in the  C PD = power dissipation capacitance (internal)  C L = capacitance of the load and wires (external) These capacitors are in parallel  C T = C PD + C L The stored charge (on these capacitors) is  Q T = C T * V DD = (C PD + C L ) * V DD

Fall 2010ECE Digital System Design11 Dynamic Power Dissipation The charge moves into and out of the capacitors on every transition of the output.  Low → High  High → Low Current = movement of charge  I AVG = (C PD + C L ) * V DD * f T Where f T = output frequency P D = I AVG * V DD = (C PD + C L ) * V 2 DD * f T

Fall 2010ECE Digital System Design12 74HC00 Datasheet

Fall 2010ECE Digital System Design13 Dynamic Power Dissipation Example: 74HC00 (Quad 2-input NAND)  V DD = 5V  C PD = 20 pF, C L = 50 pF P D = ( pF) * (5V) 2 * f T f T (Hz)P D 1K1.8  W 1M1.8 mW 100M180 mW

Fall 2010ECE Digital System Design14 74HC00 Datasheet

Fall 2010ECE Digital System Design15 Total Power Dissipation For the 74HC00, P S is determined as follows  V CC = 5V  I CC = 20  A  P S = V CC * I CC = 5V * 20  A = 100  A The P T is then determined from  P T = P S + P D  where P D is a function of f T

Fall 2010ECE Digital System Design16 Total Power Dissipation P T = P S + P D Compare P T for Quad 2-input NAND (74xx00) 0 Hz1 MHz100 MHz TTL15.8 mW15.8 mW15.8 mW CMOS100  W1.805 mW180 mW Compare TTL and CMOS TTLCMOS P S V CC * I CC V DD * I DD P D ~ 0 W(C PD + C L ) * V 2 DD * f T

Fall 2010ECE Digital System Design17 Hazards

Fall 2010ECE Digital System Design18 When the input to a combinational logic circuit changes, unwanted switching transients may appear on the output. These transients occur when different paths from input to output have different propagation delays. Hazards

Fall 2010ECE Digital System Design19 Hazards

Fall 2010ECE Digital System Design20 Hazards When analyzing combinational logic circuits for hazards we will consider the case where only one input changes at a time. Under this condition, a static 1-hazard occurs when the input change causes one product term (in a SOP expression) to transition from 1 to 0 and another product term to transition from 0 to 1. Both product terms can be transiently 0, resulting in the static 1-hazard.

Fall 2010ECE Digital System Design21 Hazards Under the same condition, a static 0-hazard occurs when the input change causes one sum term (in a POS expression) to transition from 0 to 1 and another sum term to transition from 1 to 0. Both sum terms can be transiently 1, resulting in the static 0-hazard.

Fall 2010ECE Digital System Design22 We can detect hazards in a two-level AND-OR circuit using the following procedure: 1.Write down the sum-of-products expression for the circuit. 2.Plot each term on the map and loop it. 3.If any two adjacent 1′s are not covered by the same loop, a 1-hazard exists for the transition between the two 1′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant. Detecting Static 1-Hazards

Fall 2010ECE Digital System Design23 Detecting Static 1-Hazards

Fall 2010ECE Digital System Design24 Removing Static 1-Hazards redundant, but necessary to remove hazard

Fall 2010ECE Digital System Design25 We can detect hazards in a two-level OR-AND circuit using the following procedure: 1.Write down the product-of-sums expression for the circuit. 2.Plot each sum term on the map and loop the zeros. 3.If any two adjacent 0′s are not covered by the same loop, a 0-hazard exists for the transition between the two 0′s. For an n-variable map, this transition occurs when one variable changes and the other n – 1 variables are held constant. Detecting Static 0-Hazards

Fall 2010ECE Digital System Design26 Detecting Static 0-Hazards

Fall 2010ECE Digital System Design27 Removing Static 0-Hazards How many redundant gates are necessary to remove the 0-hazards?

Fall 2010ECE Digital System Design28 Hazards Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C) = A'.C' + A.D + B.C.D'

Fall 2010ECE Digital System Design29 Hazards Exercise: Design a hazard-free combinational logic circuit to implement the following logic function F(A,B,C) = (A'+C').(A+D).(B+C+D')

Fall 2010ECE Digital System Design30 Hazards Two-level AND-OR circuits (SOP) cannot have static 1-Hazards.  Why? Two-level OR-AND circuits (POS) cannot have static 0-Hazards.  Why?

Fall 2010ECE Digital System Design31 Questions?