Face-Recognition In Intelligent Sureillence System Feng Zhao 2007 Nov.

Why We do Start from a industry Project –A more advanced DVR(Digital Video Record) –Want to integrate FR in one chip Face Recognition –High compute load –Have to Implement in PC(Cognitec “FaceVACS® ”) –Have designed a Embedded FR System on DSP –Face Recognition in a FPGA

What We have Done Embedded Solution –17fps for CIF PowerPC405 Hardware accelerator State Machine (Fully Hardware Logic) –200fps for CIF (Freq:100M)

Prototype Board Xilinx XUP Virtex-II Pro Development System (Used in “Embedded System Design” Course) Processor: PPC 405 Processor clock frequency: MHz Bus clock frequency: MHz BRAM Memory : about 200KBytes

Technology Roadmap Embedded Solution(Done ) –Powerpc405+coreConnect –Integrate Video Port to PLB Bus –XUP V2Pro Prototype Full Hardware Solution(Done ) –State Machine based –Xtream DSP –XUP V2Pro Prototype Commercial Product( ) –Based on full hardware Solution –Spartan-DSP(SA1800) –For IS’VISION Corp.(Largest FR Solution Provider) –Substitute IS’VISION’s TI DSP based solutions Multi-Channel Product(CY08) –4-Channel –D1

Solution Evaluation Start from OpenCV (Intel PC) Porting to ucLinux (Embedded SW) MicroBlaze(FSL) + HA (SW/HW) PowerPC(PLB/OPB) + HA (SW/HW) State Machine + XtremeDSP –System C level modeling –C Modeling and profiling –VerilogHDL Coding

Performance

Evaluation Conclution Embedded Solution –17fps for CIF PowerPC405 Hardware accelerator State Machine (Fully Hardware Logic) –200fps for CIF (Freq:100M)

Hardware arch for algorithm

Original PC Embedded

What Continue to do Demo on V5 Open Source