PCI-Express Network Sniffer Characterization Presentation Project Period : 2 semesters Students: Neria Wodage Aviel Tubul Advisor: Mony Orbach 17/12/2007

Motivation & Introduction The increasing demand for Internet requires a real-time monitoring & filtering system for the large amounts of data passing through the net. PCI-Express is the most common high- speed serial bus in PC computers with a performance of up to 2.5Gbps.

Project goals Developing a controlled hardware sniffer enables monitoring and filtering data on real-time and transport filtered data to the PC through the PCIe bus. Implementation of the system on Altera PCIe board with Stratix II GX FPGA.

System Environment Description Ethernet PC Stratix II GX PCIe board

Top Level Block Diagram Ethernet MAC To PC Extrnal Ethernet 10/100 Mbps 2.5 Gbps Sniffer PCIe Interface

Sniffer Abstract Diagram Sniffer Filter Control Ethernet Side Rx DATA 8-32 bit Tx DATA 8-32 bit PCIe Side Filtered Rx DATA Filter Required Parameters start\end _Packet

HW & SW Tools SW: Quartus II – Nios II – SoPC Builder - Megacore-IP library - HDL-Designer – HW: PCIe Development Board -

Tasks and schedule – part A 1. Studying basic net structure and Ethernet-TCP\IP protocols – done. 2. Learning the Altera Ethernet IP Core – in progress. 3. Learning NIOS II software environment – 20/12/07 4. Develop the Ethernet MAC block – 31/12/08 5. Execute logic simulation of the Eth. MAC – 3/1/08

6. Mid presentation 10-13/1/08 (according advisor coordination). 7. Sniffer logic design – 6/2/08 8. Performing simulation & elementary checks – 13/2/08 9. Final presentation of part A – 18-20/2/08 Tasks and schedule – part A