Recitation 9 (Nov. 8) Outline Virtual memory Lab 6 hints Reminders Lab 6: Get correctness points Exam 2: Nov. 16 (Next Tue) Minglong Shao

Slides:



Advertisements
Similar presentations
Week 12 (March 28th) Outline Memory Allocation Lab 6 Reminders Lab 6: April 7 th (next Thurs) Start Early!!! Exam 2: April 5 th (Next Tue) TA: Kun Gao.
Advertisements

Dynamic Memory Allocation
1 Dynamic Memory Allocation. 2 Outline Implementation of a simple allocator Explicit Free List Segregated Free List Suggested reading: 10.9, 10.10, 10.11,
Recitation 10 Anubhav Gupta Section D.
C SINGH, JUNE 7-8, 2010IWW 2010, ISATANBUL, TURKEY Advanced Computers Architecture, UNIT 2 Advanced Computers Architecture Virtual Memory By Rohit Khokher.
COMP 3221: Microprocessors and Embedded Systems Lectures 27: Virtual Memory - III Lecturer: Hui Wu Session 2, 2005 Modified.
Malloc & VM By sseshadr. Agenda Administration – Process lab code will be inked by Thursday (pick up in ECE hub) – Malloc due soon (Thursday, November.
Carnegie Mellon 1 Virtual Memory: Concepts : Introduction to Computer Systems 15 th Lecture, Oct. 14, 2010 Instructors: Randy Bryant and Dave O’Hallaron.
Lab 3: Malloc Lab. “What do we need to do?”  Due 11/26  One more assignment after this one  Partnering  Non-Honors students may work with one other.
Virtual Memory Oct. 21, 2003 Topics Motivations for VM Address translation Accelerating translation with TLBs class17.ppt “The course that gives.
Virtual Memory Nov 27, 2007 Slide Source: Topics Motivations for VM Address translation Accelerating translation with TLBs class12.ppt.
1 Lecture 14: Virtual Memory Topics: virtual memory (Section 5.4) Reminders: midterm begins at 9am, ends at 10:40am.
Recap. The Memory Hierarchy Increasing distance from the processor in access time L1$ L2$ Main Memory Secondary Memory Processor (Relative) size of the.
Recitation 8 (Nov. 1) Outline Lab 5 hints Virtual Memory Reminder Shell Lab: Due THIS Thursday TA: Kun Gao Modified from Minglong Shao’s Recitation, Fall.
Virtual Memory Topics Motivations for VM Address translation Accelerating translation with TLBs CS213.
Principle Behind Hierarchical Storage  Each level memorizes values stored at lower levels  Instead of paying the full latency for the “furthermost” level.
Virtual Memory October 30, 2001 Topics Motivations for VM Address translation Accelerating translation with TLBs class19.ppt “The course that gives.
Virtual Memory. Why do we need VM? Program address space: 0 – 2^32 bytes –4GB of space Physical memory available –256MB or so Multiprogramming systems.
Recitation 7 Greg Reshko Office Hours: Wed 2:00-3:00PM March 31 st, 2003.
©UCB CS 161 Ch 7: Memory Hierarchy LECTURE 24 Instructor: L.N. Bhuyan
Virtual Memory May 19, 2008 Topics Motivations for VM Address translation Accelerating translation with TLBs EECS213.
CS 241 Section Week #12 (04/22/10).
Virtual Memory Topics Motivations for VM Address translation Accelerating translation with TLBs CS 105 “Tour of the Black Holes of Computing!”
L6: Malloc Lab Writing a Dynamic Storage Allocator October 30, 2006
CML CML CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics.
University of Washington Today Lab 5 out  Puts a *lot* together: pointers, debugging, C, etc.
Carnegie Mellon /18-243: Introduction to Computer Systems Instructors: Bill Nace and Gregory Kesden (c) All Rights Reserved. All work.
1 Seoul National University Virtual Memory: Systems.
1 Recitation #9, Section F, , Sp 06 Virtual memory Reminders: Quiz today: virtual memory Shell Lab due Thursday TA: Jernej Barbic Modified from:
1 Virtual Memory: Concepts Andrew Case Slides adapted from Jinyang Li, Randy Bryant and Dave O’Hallaron.
Virtual Memory March 23, 2000 Topics Motivations for VM Address translation Accelerating address translation with TLBs Pentium II/III memory system
Malloc & VM By sseshadr. Agenda Administration – Process lab code will be inked by Thursday (pick up in ECE hub) – Malloc due soon (Thursday, November.
Virtual Memory April 3, 2001 Topics Motivations for VM Address translation Accelerating translation with TLBs class20.ppt.
University of Amsterdam Computer Systems – virtual memory Arnoud Visser 1 Computer Systems Virtual Memory.
Virtual Memory Additional Slides Slide Source: Topics Address translation Accelerating translation with TLBs class12.ppt.
Review °Apply Principle of Locality Recursively °Manage memory to disk? Treat as cache Included protection as bonus, now critical Use Page Table of mappings.
Virtual Memory.  Next in memory hierarchy  Motivations:  to remove programming burdens of a small, limited amount of main memory  to allow efficient.
Carnegie Mellon 1 Bryant and O’Hallaron, Computer Systems: A Programmer’s Perspective, Third Edition Virtual Memory: Concepts Slides adapted from Bryant.
Virtual Memory : Introduction to Computer Systems Recitation 10: Oct. 28, 2013 Marjorie Carlson Recitation A.
Virtual Memory Topics Motivations for VM Address translation Accelerating translation with TLBs CS 105 “Tour of the Black Holes of Computing!”
Carnegie Mellon Introduction to Computer Systems / Spring 2009 March 23, 2009 Virtual Memory.
CS 105 “Tour of the Black Holes of Computing!”
CSE 351 Dynamic Memory Allocation 1. Dynamic Memory Dynamic memory is memory that is “requested” at run- time Solves two fundamental dilemmas: How can.
1 Dynamic Memory Allocation (II) Implementation. 2 Outline Implementation of a simple allocator Explicit Free List Segregated Free List Suggested reading:
Virtual Memory CS740 October 13, 1998 Topics page tables TLBs Alpha 21X64 memory system.
1 Virtual Memory. 2 Outline Virtual Space Address translation Accelerating translation –with a TLB –Multilevel page tables Different points of view Suggested.
CS203 – Advanced Computer Architecture Virtual Memory.
Computer Architecture Recitation 3 Presenter: Kevin Chang Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 3/16/2015.
Today How was the midterm review? Lab4 due today.
Virtual Memory.
Virtual Memory : Introduction to Computer Systems Recitation 10: Nov. 2, 2015 Karthic Palaniappan.
Memory Hierarchy Virtual Memory, Address Translation
CSE 153 Design of Operating Systems Winter 2018
CS 105 “Tour of the Black Holes of Computing!”
Virtual Memory: Concepts /18-213/14-513/15-513: Introduction to Computer Systems 17th Lecture, October 23, 2018.
CSCI206 - Computer Organization & Programming
Nikhil, Kashish, Krishanu, Stan
CS 105 “Tour of the Black Holes of Computing!”
Virtual Memory S04, Recitation, Section A
FIGURE 12-1 Memory Hierarchy
Page that info back into your memory!
Virtual Memory CSCI 380: Operating Systems Lecture #7 -- Review and Lab Suggestions William Killian.
Virtual Memory Nov 27, 2007 Slide Source:
CS 105 “Tour of the Black Holes of Computing!”
CSCI 380: Operating Systems William Killian
CS 105 “Tour of the Black Holes of Computing!”
CS703 - Advanced Operating Systems
CSE 153 Design of Operating Systems Winter 2019
Understanding mm-helper.c Adding debugging info to mm-helper.c
Instructor: Phil Gibbons
Presentation transcript:

Recitation 9 (Nov. 8) Outline Virtual memory Lab 6 hints Reminders Lab 6: Get correctness points Exam 2: Nov. 16 (Next Tue) Minglong Shao Office hours: Thursdays 5-6PM Wean Hall 1315

Virtual memory (VM) One of the most important concepts in CS Why use virtual memory (VM) Use RAM as a cache for disk Easier memory management Access protection

Virtual memory CPU 0: 1: N-1: Memory 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses Page, page table, page hits, page faults Demand paging

Conceptual address translation Higher bits of address (page number) mapped from virtual addr. to physical addr. Lower bits (page offset) stay the same. virtual page number (VPN)page offset virtual address physical page number (PPN) page offset physical address 0p–1 address translation pm–1 n–1 0p–1p

Address translation through page table Translation Separate (set of) page table(s) per process VPN forms index into page table (points to a page table entry)

Integrating VM and cache Most caches are physically addressed Perform address translation before cache lookup Another cache: Translation Lookaside Buffer CPU TLB Lookup Cache Main Memory VAPA miss hit data Trans- lation hit miss

Address translation with TLB virtual address virtual page numberpage offset physical address n–10p–1p validphysical page numbertag validtagdata = cache hit tagbyte offset index = TLB hit TLB Cache...

Example Understand end-to-end addr. translation 20-bit virtual addresses 18-bit physical addresses Page size is 1024 bytes TLB is 2-way associative with 16 total entries

Example: TLB and page table

Part 1 A. Virtual address B. Physical address VPN VPO TLBTTLBI PPN PPO

Part 2 Virtual address 0x78E6 A. 078E6 = B. Address translation C. Physical address parameterValueParameterValue VPN0x01ETLB hit?N TLB Index0x6Page fault?N TLB Tag0x03PPN0x

Part 2 Virtual address 0x04AA4 A. 04AA4 = B. Address translation C. Physical address parameterValueParameterValue VPN0x012TLB hit?Y TLB Index0x2Page fault?N TLB Tag0x02PPN0x68

End-to-end address translation Section : a concrete example Read carefully and solve practice problem 10.4 Multi-level page table

Malloc Lab (Lab 6) Submit twice Checkpoint submission: Only check correctness: 15 pts Final submission: Correctness: 10 pts Performance: 60 pts Interposition test: 5 pts Style: 5 pts Start early!! Get correctness points this week

Design options Organize free blocks Implicit free list Explicit free list Segregate lists/search trees Find free blocks First fit/next fit Blocks sorted by address with first fit Best fit Large design space Step by step

Example implementation Section Understand every line of the code Implicit free list + immediate boundary tag coalescing + first fit Code is available at Use it as a starting point

Block format Header Pointer returned by malloc (Block Pointer (bp)) 32 bits >= what user asked for in malloc Footer Payload

Header/footer format Double word alignment Three lower-order bits of size always 0 Pack size and allocated bits into a single integer Size = 24 (0x18). Block is allocated Header = 0 x18 | 0x1 = 0x a size

Heap format 8|1 0|1 Double Word Alignment (8 bytes) 4 bytes Pad PrologueEpilogue Allocated and Free Blocks HDRFTRHDRFTR

Very useful macros #define WSIZE 4 #define DSIZE 8 #define CHUNKSIZE (1<<12) #define OVERHEAD 8

Very useful macros #define PACK(size, alloc) ((size) | (alloc)) #define GET(p) (*(size_t *)(p)) #define PUT(p, val) (*(size_t *)(p) = (val)) #define GET_SIZE(p) (GET(p) & ~0x7) #define GET_ALLOC(p) (GET(p) & 0x1)

Very useful macros #define HDRP(bp) ((char *)(bp) - WSIZE) #define FTRP(bp) ((char *)(bp) + GET_SIZE(HDRP(bp)) - DSIZE) #define NEXT_BLKP(bp) ((char *)(bp) + GET_SIZE(((char *)(bp) - WSIZE))) #define PREV_BLKP(bp) ((char *)(bp) - GET_SIZE(((char *)(bp) - DSIZE)))

Initializing the heap int mm_init(void) { if ((heap_listp = mem_sbrk(4*WSIZE)) == NULL) return -1; PUT(heap_listp, 0); PUT(heap_listp+WSIZE, PACK(OVERHEAD, 1)); PUT(heap_listp+DSIZE, PACK(OVERHEAD, 1)); PUT(heap_listp+WSIZE+DSIZE, PACK(0, 1)); heap_listp += DSIZE; if (extend_heap(CHUNKSIZE/WSIZE) == NULL) return -1; return 0; }

Extending the heap static void *extend_heap(size_t words) { char *bp; size_t size; size = (words % 2) ? (words+1)*WSIZE : words*WSIZE; if ((int)(bp = mem_sbrk(size)) < 0) return NULL; PUT(HDRP(bp), PACK(size, 0)); PUT(FTRP(bp), PACK(size, 0)); PUT(HDRP(NEXT_BLKP(bp)), PACK(0, 1)); return coalesce(bp); }

Malloc void *mm_malloc(size_t size) { size_t asize, extendsize; char *bp; if (size <= 0) return NULL; if (size <= DSIZE) asize = DSIZE+OVERHEAD; else asize = DSIZE*((size+(OVERHEAD)+(DSIZE-1))/DSIZE); if ((bp = find_fit(asize)) != NULL) { place(bp, asize); return bp; } extendsize = MAX(asize,CHUNKSIZE); if ((bp = extend_heap(extendsize/WSIZE)) == NULL) return NULL; place(bp, asize); return bp; }

Finding first fit static void *find_fit(size_t asize) { void *bp; for (bp = heap_listp; GET_SIZE(HDRP(bp)) > 0; bp = NEXT_BLKP(bp)) if (!GET_ALLOC(HDRP(bp)) && (asize <= GET_SIZE(HDRP(bp)))) return bp; return NULL; }

Malloc void *mm_malloc(size_t size) { size_t asize, extendsize; char *bp; if (size <= 0) return NULL; if (size <= DSIZE) asize = DSIZE+OVERHEAD; else asize = DSIZE*((size+(OVERHEAD)+(DSIZE-1))/DSIZE); if ((bp = find_fit(asize)) != NULL) { place(bp, asize); return bp; } extendsize = MAX(asize,CHUNKSIZE); if ((bp = extend_heap(extendsize/WSIZE)) == NULL) return NULL; place(bp, asize); return bp; }

Placing a block in a free block static void place(void *bp, size_t asize) { size_t csize = GET_SIZE(HDRP(bp)); if ((csize - asize) >= (DSIZE + OVERHEAD)) { PUT(HDRP(bp), PACK(asize, 1)); PUT(FTRP(bp), PACK(asize, 1)); bp = NEXT_BLKP(bp); PUT(HDRP(bp), PACK(csize-asize, 0)); PUT(FTRP(bp), PACK(csize-asize, 0)); } else { PUT(HDRP(bp), PACK(csize, 1)); PUT(FTRP(bp), PACK(csize, 1)); }

Free void mm_free(void *bp) { size_t size = GET_SIZE(HDRP(bp)); PUT(HDRP(bp), PACK(size, 0)); PUT(FTRP(bp), PACK(size, 0)); coalesce(bp); }

Coalesce: called by mm_free() & extend_heap() static void *coalesce(void *bp) { size_t prev_alloc = GET_ALLOC(FTRP(PREV_BLKP(bp))); size_t next_alloc = GET_ALLOC(HDRP(NEXT_BLKP(bp))); size_t size = GET_SIZE(HDRP(bp)); if (prev_alloc && next_alloc) { return bp; } else if (prev_alloc && !next_alloc) { …… } else if (!prev_alloc && next_alloc) { size += GET_SIZE(HDRP(PREV_BLKP(bp))); PUT(FTRP(bp), PACK(size, 0)); PUT(HDRP(PREV_BLKP(bp)), PACK(size, 0)); bp = PREV_BLKP(bp); } else { …… } return bp; }