EDA TOOLS

Why EDA? Imagine a Intel based micro processor having 1.5 million transistors. Would it be feasible to design such a complex system with help of truth table and K-maps? Obviously Impossible.

Continued Today’s semiconductors and electronic systems are complex that designing them would be impossible without electronic design automation (EDA). This primer provides a comprehensive over view of the electronic design process, then describes how design teams use Cadence tools to create the best possible design in the least amount of the time.

Digital Design Flow Verilog/ VHDL Library Std., Cell. Library Tech file For layout values Look up Table for timing Tech file For RC Parasite extraction Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Design Analysis This is a very crucial step in digital design where the design functionality is stated. Like if we are making a processor, what type of functionality is expected??

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Design Specification This step involved stating in definite terms the performance of the chip. Like if we are making a processor, data size, processor speed, special functions, power etc. is clearly stated at this point. Also somewhat it is decided, the way to implement the design. So, it deals with architectural part of the design at highest level possible. Based on these foundation, the whole design is built

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification HDL Hardware Description Language is used to run the simulations. It is very expensive to build the entire chip and then verify the performance of the architecture. Imagine if after designing a chip for a whole year, the chip fabricated, does not come even closer to the stated specifications.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification HDL (contd.) Hardware description languages provides a way to implement a design without going into much architecture, simulate and verify the design output and functionality. For eg. rather than building a mux design in hardware, we can write verilog code and verify the output at higher level of abstraction. Examples of HDL: VHDL, Verilog HDL

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification HDL (Contd.) At this time we can see the design in the form of Source Codes. It seems more of the software visualization of the circuit. The simulated code is taken to Synthesis to generate the Logic Circuit.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis Imagine the use of K-Maps and Truth Tables to make and implement a digital design. If you notice, most of the digital designs are build up of some basic elements or components like gates, registers, counters, adders, subtractors, comparators, RAM, ROM etc. It forms the fundamentals of Logic Synthesis using EDA tools.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis (Contd.) Standard Cell Library is the collection of such building blocks which comprises most of the digital designs. These cell libraries are fabrication technology specific.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis ( Contd.) After the RTL simulation, the HDL, code is taken as input by Synthesis Tool and converted to Gate level. At this stage that the digital design becomes dependent on the fabrication process. At the end of this stage, we have the logic circuit I.e. in terms of gates and memories.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis ( Contd.) What synthesis does is, when it encounters a specific construct in HDL it replaces it with the corresponding Standard Cell Component from the library to build the entire design. Like if we use a for loop, it gets converted to counter and a combinational circuit.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Synthesis ( Contd.) The output of synthesis is a gate level netlist. Netlist is an ASCII file which enlists and indicates the devices and the interconnections between them.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Simulation After the netlist is generated as part of synthesis, this netlist is simulated to verify the functionality of this gate level implementation of design. Till this level we just dealt with functionality part. Now each step onward deals with performance part too.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis RTL and Gate Level simulation doesn’t take into account the physical time delay in signal propagation from one device to another and through the device. This time delay is dependent on the fabrication process adopted.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis (Contd.) Each component in standard cell library is associated with some specific delay. Delay Lookup Tables list the delays associated with the components. Delays are in the form of rise time, fall time and turn off time delays.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis (Contd.) Most of the digital designs employ concept of timing by using clocks. This makes the circuits synchronous. Consider an AND gate with two inputs, x and y. If at time t = 1 ns, x is available, and y comes 1 ns later, what would be the output. This mismatch in timing leads to erroneous performance of design.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Timing Analysis (Contd.) In timing analysis, using Delay Lookup Tables, all the inputs and outputs of components are verified with timing introduced.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Place & Route This is the actual stage where the design implemented at semiconductor layout level. This the stage which really requires more knowledge of semiconductor physics than digital design.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Place & Route (Contd.) Semiconductor layout has to follow certain design rules to lay devices at semiconductor level. These design rules are fabrication process dependent. The layout uses layers as p/n diffusion, nwell, pwell, metals, via, iso etc. Rules involving min. spacing, and electrical relation between two layers are known as DESIGN RULES.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Place & Route (Contd.) Placement and Routing involves laying of the devices, placing them and making interconnection between them, following the Design Rules. The result is the design implemented in the form of semiconductor layers.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Extraction Once the layout is made, there always is parasitic capacitances and resistances associated with the design. This is because of the compact layouts to make the chips smaller. More you make compact layout more will it introduce these parasitic components. These interferes in the functioning and performance of the circuit in terms of timing, speed and power consumption.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Extraction (Contd.) Due to these factors it becomes very much important to extract these devices from layout and check the design for performance and functionality. Extraction would extract from the layout, the devices formed because of junctions of different semiconductor and metal layers and the interconnections.

Design Analysis Design Specification Synthesis Design Implementation using HDL Simulation Timing Analysis Place & Route Extraction Verification Verification would either be the tape out stage of the chip or the stage where design is again taken back through the same flow for optimization or modification. It verifies the extracted view of the chip for performance and functionality.

Major Companies in EDA Tools Cadence Design Systems Synopsys Avanti Tanner

Cadence is the world's largest provider of electronic design automation (EDA) products and services. Our end-to-end solutions help computer, communication, and consumer electronics companies create high- performance systems and integrated circuits (ICs) in the shortest possible time. Cadence is a global company with 5,700 employees in over 30 major locations, and revenues of nearly $1.3 billion in Cadence Fact sheet

History of Cadence Cadence Design Systems, Inc. was established in 1988 through the merger of two EDA pioneers—ECAD, Inc. and SDA Systems. Through innovative product development, strategic partnerships, and highly successful business mergers, Cadence has become the industry's leading supplier of EDA software technology and services.

System-level Design Functional Verification Emulation and Acceleration Synthesis/Place-and-Route Analog, RF, and Mixed-signal Design Custom IC Layout Physical Verification and Analysis IC Packaging PCB Design Cadence Design Technologies

Cadence Design Flow Digital Design: Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog

Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog NC-Family of Simulators The Cadence NC family of simulators (NC-Sim, NC- Verilog®, NC-VHDL and the Verilog® and VHDL Desktop simulators) provides a single- kernel simulator that can verify both mixed-language and mixed- signal designs.

NC – Verilog (Contd.) Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog Advantage Works on the principle of Native Compilation. Unlike other compilers it compiles HDL code directly to machine executable codes, rather than going through the intermediate conversion to C. It decreases: Compilation time, Memory requirement and use of system resources

NC – Verilog (Contd.) Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog Key Features Fastest mixed-language simulation available due to unique NC architecture Powerful integrated debug and analysis environment Mixed-language, mixed-signal, and system-level support

Ambit Buildgates Synthesis Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog Key Features BuildGates® Synthesis can synthesize multimillion-gate designs very rapidly. BuildGates features high-capacity and high-performance timing analysis..

Ambit Buildgates Synthesis Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog BuildGates® Synthesis can synthesize multimillion-gate designs very rapidly. BuildGates features high-capacity and high-performance timing analysis..

Ambit Buildgates Synthesis Contd. Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog Key Features Provides productive multimillion- gate synthesis through higher capacity and faster runtimes Delivers accuracy and reduced iterations through integrated sign- off static timing analysis Reduces IC power consumption with the Low-power Synthesis Option.

Ambit Buildgates Synthesis Contd. Standard Cell Library Pearl Static Timing Analysis Silicon Ensemble Placement & Route Hyper Extract Tech. Rules verification Ambit Synthesis NC-Verilog Optimized Design It can optimize the design for: Speed Size Power Consumption.

Static Timing Analysis (Pearl) In this era of high performance electronics, timing continues to be a top priority and designers are spending increased effort addressing IC performance. Two Methods are employed for Timing Analysis: Dynamic Timing Analysis Static Timing Analysis

Static Timing Analysis (Pearl) (Contd.) Traditionally, a dynamic simulator has been used to verify the functionality and timing of an entire design or blocks within the design. Dynamic timing simulation requires vectors, a logic simulator and timing information. With this methodology, input vectors are used to exercise functional paths based on dynamic timing behaviors for the chip or block. Dynamic Timing Analysis

Static Timing Analysis (Pearl) (Contd.) The advent of larger designs and mammoth vector sets make dynamic simulation a serious bottleneck in design flows. Dynamic simulation is becoming more problematic because of the difficulty in creating comprehensive vectors with high levels of coverage. Time-to-market pressure, chip complexity, limitations in the speed and capacity of traditional simulators -- all are motivating factors for migration towards static timing techniques. Dynamic Timing Analysis: Limitations

Static Timing Analysis (Pearl) (Contd.) STA is an exhaustive method of analyzing, debugging and validating the timing performance of a design. First, a design is analyzed, then all possible paths are timed and checked against the requirements. Since STA is not based on functional vectors, it is typically very fast and can accommodate very large designs (multimillion gate designs). STA is exhaustive in that every path in the design is checked for timing violations.

Static Timing Analysis (Pearl) (Contd.) Limitations: STA does not verify the functionality of a design. Also, certain design styles are not well suited for static approach. For instance, dynamic simulation may be required for asynchronous parts of a design and certainly for any mixed-signal portions.

Silicon Ensemble Place & Route

Future Trends Verilog AMS CCAR (Cadence Chip Assemble Router) VCC Testbuilder for Verification PKS (Physically Knowledgeable Synthesis) ATS