StaticRoute: A novel router for the dynamic partial reconfiguration of FPGAs Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt 2/9/2013

Dynamic partial reconfiguration (DPR) 1 Advantages: Smaller area Lower power usage M1M1 M2M2 M3M3 Goal: area reduction with reduced reconfiguration time M1M1 M2M2 M3M3 Disadvantage: Reconfiguration time

Conventional DPR tool flow Different circuits are implemented independently Complete area is rewritten  Problem: long reconfiguration times 2

Static vs dynamic bits After implementation: – Each memory cell corresponds to a collection of bit values – This collection of bit values is called a static bit, when the values are the same for all circuits a dynamic bit, otherwise 3

Clustering of dynamic bits Only memory cells that contain a dynamic bit need to be rewritten during run-time Configuration memory of an FPGA is frame-based Dynamic bits are scattered over the frames Approach in this work: – Divide configuration frames into dynamic and static ones – Cluster dynamic bits into the dynamic frames 4

CLBs vs routing In our experiments: – 10% of the configuration memory consists of CLB bits – 90% of the configuration memory consists of routing bits  Most of the time spent in reconfiguring the routing infrastructure Focus on reducing reconfiguration time of routing – All CLB frames are dynamic – Routing frames are divided in static and dynamic ones – Novel router, called StaticRoute, that clusters dynamic routing bits in the dynamic routing frames 5

Proposed DPR tool flow 6

PathFinder Makes use of a routing resource graph (RRG): directed graph where nodes represent wires and edges represent routing switches For each net PathFinder finds a minimum cost tree in the RRG In a first iteration nets are allowed to share resources, i.e. wire congestion is allowed Negotiated congestion Cost function of a node in the RRG: 7

StaticRoute Extended Pathfinder algorithm that also clusters dynamic routing bits into dynamic routing frames Makes use of an extended routing resource graph (eRRG): – switches are also represented by nodes – mark switches as static/dynamic – keep information about the switches during routing Detecting dynamic bits – After routing: easy – During routing: not obvious 8

Detecting dynamic bits 9 In general, in the extended RRG, a switch node S connects two wire nodes W in and W out. Let us assume that S is used by a set of circuits C S. W in and W out are used by Cin and C out respectively. We state that S is controlled by a dynamic bit if: ((C S ̸=C in ) ∨ (C S ̸=C out )) ∧ C S ̸=φ.

Novel cost function StaticRoute Switch congestion: when a static switch is controlled by a dynamic bit StaticRoute iterates until both wire and switch congestion are resolved Novel cost function: 10

Switch congestion penalty 11 p

Experiments 12 Regular expression matching, adaptive filtering, general MCNC and MCNC20 benchmarks LBs Considered only 2 circuits at a time Comparison of conventional DPR and new flow that uses StaticRoute Metrics: Reconfiguration time Wire length (of each circuit separately)

Results – Reconfiguration time 13

Results – Reconfiguration time 14

Results – Wire length 15

Conclusions 16 Possible to detect dynamic bits during routing Introduced notion of switch congestion Novel router, called StaticRoute, that resolves both wire and switch congestion Using novel DPR tool flow that uses StaticRoute: Total reconfiguration speed-up of approx. 2X Increase in wire length is limited

StaticRoute: A novel router for the dynamic partial reconfiguration of Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt 2/9/2013