Chap. 2 Hierarchical Modeling Concepts. 2 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components.

Slides:

Advertisements

Similar presentations

Xilinx 6.3 Tutorial Integrated Software Environment (ISE) Set up basic environment Select Gates or Modules to Be simulated (Insert Program Code) Run Waveform.

Advertisements

Verilog HDL -Introduction

Simulation executable (simv)

Verilog Overview. University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.

Chap. 6 Dataflow Modeling

CPEN Digital System Design

Verilog Intro: Part 1.

Anurag Dwivedi.  Verilog- Hardware Description Language  Modules  Combinational circuits  assign statement  Control statements  Sequential circuits.

SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part3: Verilog – Part 1.

CSE 201 Computer Logic Design * * * * * * * Verilog Modeling

Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.

CSE 341 Verilog HDL An Introduction. Hardware Specification Languages Verilog  Similar syntax to C  Commonly used in  Industry (USA & Japan) VHDL 

1 Lecture 1: Verilog HDL Introduction. 2 What is Verilog HDL? Verilog Hardware Description Language(HDL)? –A high-level computer language can model, represent.

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu.

1 Hardware description languages: introduction intellectual property (IP) introduction to VHDL and Verilog entities and architectural bodies behavioral,

CSE241 R1 Verilog.1Kahng & Cichy, UCSD ©2003 CSE241 VLSI Digital Circuits Winter 2003 Recitation 1: Verilog Introduction.

Reconfigurable Computing (EN2911X, Fall07) Lecture 05: Verilog (1/3) Prof. Sherief Reda Division of Engineering, Brown University

Digital System Design Verilog ® HDL Modules and Ports Maziar Goudarzi.

Digital System Design Verilog ® HDL Maziar Goudarzi.

Spring 2002EECS150 - Lec0-intro Page 1 EECS150 - Digital Design Lecture 8 - Hardware Description Languages February 14, 2002 John Wawrzynek.

Hardware Description Language(HDL). Verilog simulator was first used beginning in 1985 and was extended substantially through The implementation.

L16 – Testbenches for state machines. VHDL Language Elements  More examples HDL coding of class examples Testbench for example  Testing of examples.

Introduction Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL) A hardware description language is a language or means used to describe or model a digital.

CS 3850 Lecture 3 The Verilog Language. 3.1 Lexical Conventions The lexical conventions are close to the programming language C++. Comments are designated.

CS 61C L4.2.2 Verilog II (1) K. Meinz, Summer 2004 © UCB CS61C : Machine Structures Lecture Verilog II Kurt Meinz inst.eecs.berkeley.edu/~cs61c.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 3: Structural Modeling Spring 2009 W. Rhett.

Digital System 數位系統 Verilog HDL Ping-Liang Lai (賴秉樑)

Language Concepts Ver 1.1, Copyright 1997 TS, Inc. VHDL L a n g u a g e C o n c e p t s Page 1.

Digital System Design Introduction to Verilog ® HDL Maziar Goudarzi.

Module 2.1 Gate-Level/Structural Modeling UNIT 2: Modeling in Verilog.

CH71 Chapter 7 Hardware Description Language (HDL) By Taweesak Reungpeerakul.

1/8/ L7 Project Step 3Copyright Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement.

1 CSE-308 Digital System Design (DSD) N-W.F.P. University of Engineering & Technology, Peshawar.

1 COMP541 Sequential Circuits Montek Singh Feb 1, 2012.

Chap. 4 Modules and Ports. 2 Modules and Ports Modules Ports Hierarchical Names Summary.

1 component OR_3 port (A,B,C: in bit; Z: out bit); end component ; Reserved Words  Declarations of Components and Entities are similar  Components are.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics Modeling with hardware description languages (HDLs).

Modern VLSI Design 3e: Chapter 8 Copyright  1998, 2002 Prentice Hall PTR Topics n Modeling with hardware description languages (HDLs).

Switch Level Modeling Part II 26 September Contents 1.Clarifications: a)nMOS and pMOS instantiations b)Testbenches for NOR gate example c)Use of.

Digital System Design Verilog ® HDL Design at Structural Level Maziar Goudarzi.

LECTURE VII SECTION 4.12 PART 1 MODELS OF COMBINATIONAL CIRCUITS.

Verilog A Hardware Description Language (HDL ) is a machine readable and human readable language for describing hardware. Verilog and VHDL are HDLs.

CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 4: Testing, Dataflow Modeling Spring 2009.

FPGA-Based System Design Copyright  2004 Prentice Hall PTR Topics n Modeling with hardware description languages (HDLs).

Chapter 6: Hierarchical Structural Modeling Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 6-1 Chapter 6: Hierarchical.

Chapter1: Introduction Digital System Designs and Practices Using Verilog HDL and 2008~2010, John Wiley 1-1 Chapter 1: Introduction Prof. Ming-Bo.

Verilog Intro: Part 1. Hardware Description Languages A Hardware Description Language (HDL) is a language used to describe a digital system, for example,

1 University of Jordan Computer Engineering Department CPE 439: Computer Design Lab.

1 Lecture 1: Verilog HDL Introduction. 2 What is Verilog HDL? Verilog Hardware Description Language(HDL)? –A high-level computer language can model, represent.

Structural Description

Supplement on Verilog FF circuit examples

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu.

Verilog Introduction Fall

Topics Modeling with hardware description languages (HDLs).

Hardware Description Languages

Topics Modeling with hardware description languages (HDLs).

Introduction To Verilog-HDL

Introduction to Verilog® HDL

Designing with Verilog

Register-Transfer Level Components in Verilog

Verilog-HDL Reference: Verilog HDL: a guide to digital design and synthesis, Palnitkar, Samir Some of slides in this lecture are supported by Prof. An-Yeu.

Supplement on Verilog adder examples

The Verilog Hardware Description Language

CS 153 Logic Design Lab Professor Ian G. Harris

Introduction to Verilog® HDL

Introduction to Digital IC Design

Reconfigurable Computing (EN2911X, Fall07)

Presentation transcript:

Chap. 2 Hierarchical Modeling Concepts

2 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

3 Design Methodology Top-down design methodology  Define the final (top) module  Analyze the components which are composed of top module step by step Bottom-up design methodology  Design the basic components  Assemble basic components to larger design until the top design is completed

4 Top-down Design Methodology

5 Bottom-up Design Methodology

6 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

7 4-bit Ripple Carry Counter

8 Hierarchy of 4-bit Ripple Carry Counter Top-down Bottom-up

9 Basic Component: T Flip-Flop

10 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

11 Modules Basic component in Verilog for describing/defining a hardware module ( ); … … endmodule

12 A module for T F.F. module T_FF (q, clock, reset); … … endmodule

13 Levels of functionality Behavioral (algorithmic) level Dataflow level Gate level Switch level

14 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

15 Instances Individual object of module  Module is similar to “function declaration” in C, and instance likes the concept of “function call” Instantiation  A procedure of constructing an instance using module

16 Instances and Instantiation - I Instantiation Instances tff0, tff1, tff2, tff3

17 Instances and Instantiation - II

18 Illegal Module Declaration (Nested module)

19 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

20 Components of a Simulation Design Under Test (DUT) － Design Block Test bench － Stimulus Block  Stimulus generation  Output checking

21 Instantiate a design under test (dut). Stimulus Block - I

22 Additional top module instantiating stimulus and design block. Stimulus Block - II

23 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

24 A Complete Example of 4-bit Ripple Carry Counter

25 T Flip-Flop

26 D Flip-Flop

27 Stimulus and Output Waves

28 Stimulus Block (Testbench)

29 Simulation results

30 Hierarchical Modeling Concepts Design Methodologies 4-bit Ripple Carry Counter Modules Instances Components of a Simulation Example Summary

31 Summary Top-down v.s bottom-up design methodologies Module is basic construction block in Verilog Instance is individual object created by module A simulation consists of two components: Design Block and Stimulus Block