ECE2030 Introduction to Computer Engineering Lecture 3: Switches and CMOS Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia.

Slides:

Advertisements

Similar presentations

Physical structure of a n-channel device:

Advertisements

(Neil weste p: ).  A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain.

Chapter 6 The Field Effect Transistor

MOSFETs Monday 19 th September. MOSFETs Monday 19 th September In this presentation we will look at the following: State the main differences between.

Lecture 11: MOS Transistor

VLSI Design EE213 VLSI DesignStephen Daniels 2003 R Vss R Vo Inverter : basic requirement for producing a complete range of Logic circuits.

Lecture #26 Gate delays, MOS logic

Spring 2007EE130 Lecture 35, Slide 1 Lecture #35 OUTLINE The MOS Capacitor: Final comments The MOSFET: Structure and operation Reading: Chapter 17.1.

10/8/2004EE 42 fall 2004 lecture 171 Lecture #17 MOS transistors MIDTERM coming up a week from Monday (October 18 th ) Next Week: Review, examples, circuits.

Lecture 15 OUTLINE MOSFET structure & operation (qualitative)

Computer Engineering 222. VLSI Digital System Design Introduction.

(N-Channel Metal Oxide Semiconductor)

The metal-oxide field-effect transistor (MOSFET)

Chapter 5 – Field-Effect Transistors (FETs)

Introduction to CMOS VLSI Design Lecture 3: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2004 from CMOS VLSI Design A Circuits and Systems.

Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley.

Lecture #25 Timing issues

Design and Implementation of VLSI Systems (EN1600) lecture02 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Chap. 5 Field-effect transistors (FET) Importance for LSI/VLSI –Low fabrication cost –Small size –Low power consumption Applications –Microprocessors –Memories.

Dr. Nasim Zafar Electronics 1 - EEE 231 Fall Semester – 2012 COMSATS Institute of Information Technology Virtual campus Islamabad.

Lecture 2: CMOS Transistor Theory

VLSI design Lecture 1: MOS Transistor Theory. CMOS VLSI Design3: CMOS Transistor TheorySlide 2 Outline  Introduction  MOS Capacitor  nMOS I-V Characteristics.

ECEN 248: INTRODUCTION TO DIGITAL SYSTEMS DESIGN Lecture 5 Dr. Shi Dept. of Electrical and Computer Engineering.

10-7 Metal-Oxide Semiconductor （ MOS ）  Field-Effect Transistor （ FET ） Unipolar transistor Depend on the flow of only one type of carrier JFET, MOS 

Transistor Characteristics EMT 251. Outline Introduction MOS Capacitor nMOS I-V Characteristics (ideal) pMOS I-V Characteristics (ideal)

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

MOS Capacitors ECE Some Classes of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor ▫ MOSFET, which will be the type that.

CSET 4650 Field Programmable Logic Devices

Metal-Oxide-Semiconductor Field Effect Transistors

Lecture 19 OUTLINE The MOSFET: Structure and operation

Lecture 3: CMOS Transistor Theory

ECE 331 – Digital System Design Transistor Technologies, and Realizing Logic Gates using CMOS Circuits (Lecture #23)

Transistors Three-terminal devices with three doped silicon regions and two P-N junctions versus a diode with two doped regions and one P-N junction Two.

Digital Integrated Circuits© Prentice Hall 1995 Introduction The Devices.

Chapter 5: Field–Effect Transistors

Qualitative Discussion of MOS Transistors. Big Picture ES220 (Electric Circuits) – R, L, C, transformer, op-amp ES230 (Electronics I) – Diodes – BJT –

MOS Transistors The gate material of Metal Oxide Semiconductor Field Effect Transistors was original made of metal hence the name. Present day devices’

1 Metal-Oxide-Semicondutor FET (MOSFET) Copyright  2004 by Oxford University Press, Inc. 2 Figure 4.1 Physical structure of the enhancement-type NMOS.

Qualitative Discussion of MOS Transistors. Big Picture ES230 – Diodes – BJT – Op-Amps ES330 – Applications of Op-Amps – CMOS Analog applications Digital.

Class 02 DICCD Transistors: Silicon Transistors are built out of silicon, a semiconductor Pure silicon is a poor conductor (no free charges) Doped.

Field Effect Transistors: Operation, Circuit Models, and Applications AC Power CHAPTER 11.

Field Effect Transistor. What is FET FET is abbreviation of Field Effect Transistor. This is a transistor in which current is controlled by voltage only.

NOTES 27 March 2013 Chapter 10 MOSFETS CONTINUED.

ECE340 ELECTRONICS I MOSFET TRANSISTORS AND AMPLIFIERS.

ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech.

1 Chapter 5. Metal Oxide Silicon Field-Effect Transistors (MOSFETs)

UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY

Chapter 12 : Field – Effect Transistors 12-1 NMOS and PMOS transistors 12-2 Load-line analysis of a simple NMOS amplifier 12-3 Small –signal equivalent.

EE210 Digital Electronics Class Lecture 7 May 22, 2008.

ISAT 436 Micro-/Nanofabrication and Applications Transistors David J. Lawrence Spring 2004.

Introduction to MOS Transistors Section Selected Figures in Chapter 15.

Introduction to CMOS EE2174 Digital Logic and Lab Dr. Shiyan Hu

 Seattle Pacific University EE Logic System DesignNMOS-CMOS-1 Voltage-controlled Switches In order to build circuits that implement logic, we need.

Introduction to MOS Transistors Section Outline Similarity Between BJT & MOS Introductory Device Physics Small Signal Model.

11. 9/15 2 Figure A 2 M+N -bit memory chip organized as an array of 2 M rows  2 N columns. Memory SRAM organization organized as an array of 2.

CMOS VLSI Design CMOS Transistor Theory

Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris Harvey Mudd College Spring 2007.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 19, 2014 MOS Transistor.

EECS 270: Inside Logic Gates (CMOS)

1 Other Transistor Topologies 30 March and 1 April 2015 The two gate terminals are tied together to form single gate connection; the source terminal is.

EE Electronics Circuit Design Digital Logic Gates 14.2nMOS Logic Families 14.3Dynamic MOS Logic Families 14.4CMOS Logic Families 14.5TTL Logic.

Introduction to CMOS Transistor and Transistor Fundamental

1 ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network Prof. Hsien-Hsin Sean Lee School of ECE Georgia Institute of Technology.

CP 208 Digital Electronics Class Lecture 6 March 4, 2009.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 10: September 20, 2013 MOS Transistor.

MOSFET V-I Characteristics Vijaylakshmi.B Lecturer, Dept of Instrumentation Tech Basaveswar Engg. College Bagalkot, Karnataka IUCEE-VLSI Design, Infosys,

Field Effect Transistors: Operation, Circuit Models, and Applications

ECE2030 Introduction to Computer Engineering Lecture 4: CMOS Network

Basic electrical properties

Prof. Hsien-Hsin Sean Lee

Presentation transcript:

ECE2030 Introduction to Computer Engineering Lecture 3: Switches and CMOS Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2 2 Basic Switch pathA path exists when the Switch Control is closed open (OFF) –If (Open) OUTPUT = unknown ; Switch is open (OFF) closed –Else OUTPUT = INPUT ; Switch is closed (ON) INPUT OUTPUT Switch Control

3 3 The Analogy of A Transistor Cross Section An N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) INPUT OUTPUT Switch Control (Gate)

4 4 Transistor Characteristics Cut-offCut-off Region –Vgs – Vt  0 –No current (Ids) between drain and source LinearLinear (or Ohmic) Region –0 < Vds < Vgs – Vt –Ids is a function of Vgs and Vds –Ids = β*[(Vgs-Vt)*Vds – Vds*Vds/2] SaturationSaturation Region –0 < Vgs – Vt < Vds –Ids is independent of Vds –Ids = (β/2)*(Vgs-Vt) 2 –β = process factor * (W/L) VtVt : Threshold voltage, a function of materials, doping, insulator thickness, etc. Gate Drain Source Ids Vds Vgs N-type MOS Transistor

5 5 Transistor Characteristics

6 6 Switches in Series INPUT OUTPUT S1 S2 Truth Table S1S2PATH? OFF ON OFF ON

7 7 Switches in Series INPUT OUTPUT S1 S2 Truth Table (OFF/ON=0/1) S1S2PATH? OFF NO OFFONNO ONOFFNO ON YES What Function ??

8 8 Switches in Series INPUT OUTPUT S1 S2 Truth Table (OFF/ON=0/1) S1S2PATH? 000 Function = ??

9 9 Switches in Series INPUT OUTPUT S1 S2 Truth Table (OFF/ON=0/1) S1S2PATH? Function = ??

10 Switches in Series INPUT OUTPUT S1 S2 Truth Table (OFF/ON=0/1) S1S2PATH? Function = ??

11 Switches in Series INPUT OUTPUT S1 S2 Truth Table (OFF/ON=0/1) S1S2PATH? AND Function = Logic AND

12 Switches in Parallel INPUT OUTPUT S1 Truth Table S1S2PATH? OFF NO OFFONYES ONOFFYES ON YES S2

13 Switches in Parallel INPUT OUTPUT S1 Truth Table S1S2PATH? 000 Function =?? S2

14 Switches in Parallel INPUT OUTPUT S1 Truth Table S1S2PATH? Function =?? S2

15 Switches in Parallel INPUT OUTPUT S1 Truth Table S1S2PATH? Function =?? S2

16 Switches in Parallel INPUT OUTPUT S1 Truth Table S1S2PATH? OR Function = Logic OR S2

17 CMOS Transistor Complementary MOS –P-channel MOS (pMOS) –N-channel MOS (nMOS) pMOS –P-type source and drain diffusions –N substrate –Mobility by holes nMOS –N-type source and drain diffusions –P substrate –Mobility by electrons Gate Drain Source Gate Source Drain pMOS nMOS

18 Pass Transistor using NMOS Assume capacitor (C L ) is initially discharged Gate=1, Vin=1 –C L begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt) –Signal is degraded Gate=Vdd Vin=Vdd Vout Ground Load Capacitor Vgs I Gate=Vdd Vin=0 Vout=Vdd Ground Load Capacitor Vgs I Gate=1, Vin=0 –C L begins to discharge toward 0 –

19 Transmission Degradation using Pass Transistor Vdd - Vt Vdd Vdd (1) Vdd - 2Vt Vdd Vout = Vdd- N*Vt Still 1??

20 CMOS Signal Transfer Property GatePath 0Closed 1Open Gate Drain Source Gate Source Drain GatePath 0Open 1Closed pMOS nMOS Transmits 1 well Transmits 0 poorly Transmits 0 well Transmits 1 poorly

21 CMOS Transmission Gate Transmit signal from INPUT to OUTPUT when Gate is closed complementary of Gate Gate (complementary of Gate) SourceDrain Gate INPUT OUTPUT GatepMOSnMOSOUTPUT 0OFF Z 1ON INPUT Z Z : High-Impedance State, consider the terminal is “floating”

22 High Impedance When a path exists –Impedance is low to allow ample flow of current When no path –Impedance is high allowing almost no current flow between two terminals Gate=1 Drain Source << 10K  >> 100M  Closed Gate=0 Drain Source Open

23 Transmission Gates Gate = Gate = 0 Transmit Logic 0 Gate = Gate = 0 Transmit Logic 1

24 Transmission Gate Symbol Gate INPUT OUTPUT Gate INPUT OUTPUT 