Wilga 2006 Pi of the Sky data transmission Janusz Użycki Faculty of Physics Warsaw University of Technology.

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Presentation transcript:

Wilga 2006 Pi of the Sky data transmission Janusz Użycki Faculty of Physics Warsaw University of Technology

Wilga Agenda First cameras data exchanging interface New needs, reasons of Ethernet usage Problems with full TCP/IP stack Solutions, basic protocols of the stack Our own protocol – NUDP (in details) Simulator of the camera and driver Results

Wilga Data streaming By a medium we need to: send commands into camera get and set parameters read values from sensors receive data (i.e., send it from cameras RAM to computer)

Wilga Beginning Only 2 cameras for data/photos acquisition Every computer (one of two) controls one camera USB interface, 3 endpoints: commands from computer (EP1), data input / output Mainly bytes long command structure for example: focus motor control cmd, steps number in left direction, MSB and LSB value, repsectively 0x04 | 0x01 | 0x00 | 0x05

Wilga Needs to obtain Several cameras (4x4 matrix x 2) Parrarel work and processing More computers for analysis (something like a cluster of computers) Independence cameras from computers during accidental failure of our system Computers and cameras require unique addressing – personality

Wilga MAC address for every device 1Gbit/s data flow rate possible Low cost of connections and infrastructure Good availabity network devices like switches Checked technology, reliability Ready chips on the market, eg. Realtek chipsets Ethernet Ethernet network USB PC Camera FPGA Altera 8051 Cypress CCD block motors DRAM NIC Realtek sensors EEPROM power system

Wilga Ethernet in practice Ethernet allows to transmit own packets Absence of packet receiving control mechanism The best solution for compatibility with network switches (not hubs) IP protocol needed IP makes a way for TCP and UDP transport protocols – full TCP/IP stack needed?

Wilga TCP/IP stack First solution: usage minimalized TCP/IP stack with TCP, but camera is based on 8051 microcontroller (slow) and FPGA A second: giving up TCP, only UDP protocol which is very simple Used ethernet controller in the camera automatically calculates not only CRC of ethernet packets but checksums of IP, TCP and UDP protocols in their header!

Wilga Our simple stack model Blocks of data stream: 8248 packets filled by 1024 bytes of RAW data every – a photo Ethernet frames (MAC address) IP frames (IP address) and ICMP packets (only echo supported – ping) UDP packets as transport layer

Wilga UDP limitations Advantages: One from plenty UDP ports under one IP Optional data checksum available Disadvantages: UDP datagram does not ensure receiving one by recipient A sequence of received packets can be accidental and depends on network traffic

Wilga NUDP advantages Simple sensor network model, simplicited camera controller (everything in driver) Achieved packet receiving control by cameras acknowledgements It allows to save an order of packets There is possible retransmission of lost packets Close to compatibility with USB commands structure in EP1

Wilga The latest NUDP structure (rev ) NUDP header always contains 8 bytes: Identification field Type field of NUDP frame NUDP header checksum Number field – it is multi-function field

Wilga NUDP type field

Wilga Types of NUDP packet 0 – command, it is starting from number field 4 – set a 16-bits register (RFU) 5 – read a 16-bits register (RFU) 6 – retransmission of RAW data packet 7 – transmission of RAW data packet, it is never acknowledged and generated by camera only Other numbers of type are reserved (RFU)

Wilga How is NUDP working? (1) Selected examples of commands in practice, the most popular types of NUDP frames: Parameter setting (shutter time setting to 10s: 10000ms / 10ms = 0x3E8) PC: 0xFF 0x00 | 0x00 | 0x13 | 0x02 0x03 0xE8 0x00 Camera: 0xFF 0x00 | 0x80 | 0x93 | 0x02 0x03 0xE8 0x00 Parameter reading, device recognizing etc. (status and temperatures reading) PC: 0xFF 0x00 | 0x00 | 0xF6 | 0x0A 0x00 0x00 0x00 Camera: 0xFF 0x00 | 0x80 | 0x76 | 0x0A 0x00 0x00 0x00 | 0x1E 0x00 0x51 0x4C

Wilga How is NUDP working? (2) Watchdog reset PC: 0xFF 0x00 | 0x00 | 0x04 | 0xFC 0x00 0x00 0x00 Camera: 0xFF 0x00 | 0x80 | 0x84 | 0xFC 0x00 0x00 0x00 A photo making (start CCD readout) PC: 0xFF 0x00 | 0x00 | 0xFD | 0x03 0x00 0x00 0x00 Camera: 0xFF 0x00 | 0x80 | 0x7D | 0x03 0x00 0x00 0x00 Transmission demand (start RAW data dumping) PC: 0xFF 0x00 | 0x00 | 0xF8 | 0x08 0x00 0x00 0x00 Camera: 0xFF 0x00 | 0x80 | 0x78 | 0x08 0x00 0x00 0x00

Wilga How is NUDP working? (3) Transmission of RAW data 8248 packets with the following structure: Camera: 0xFF 0x00 | 0x07 | 0xF7 | 0x02 0x00 0x00 0x00 | Retransmission of RAW data packet PC: 0xFF 0x00 | 0x06 | 0xF8 | 0x02 0x00 0x00 0x00 Camera: 0xFF 0x00 | 0x86 | 0x78 | 0x02 0x00 0x00 0x00 |

Wilga Simulator and driver Linux system was chosen naturally NUDPSIM simulator was created for making and testings a new driver faster before camera with Ethernet was made For documentation and idea of the NUDP protocol checking programmers of the driver have not seen a source code of the simulator

Wilga Results Camera with the driver testings Ethernet network infrastructure: 1Gbit/s Achieved performance: about 100Mbits/s Under Windows all packets were received Under Linux not, a feasible reason is the driver which is not a part or module of the kernel; some packets are losing between layers (kernel UDP timeout), even after debugging off The transfer depends on a network traffic – the loading has an important influence

Wilga Summary USB was maintained next to Ethernet Some commands from USB were given up in the NUDP implementation (eg. flashing) Ethernet network USB PC Camera FPGA Altera 8051 Cypress CCD block motors DRAM NIC Realtek sensors EEPROM power system

Wilga Summary USB was maintained next to Ethernet Some commands from USB were given up in the NUDP implementation (eg. flashing) Main aims were achieved but it will be checked in longer period of the time in practice The future: an implementation a TCP protocol by NIOS usage (Altera core) at FPGA chip and a RTOS