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2 Charge-Based DRAM Cell The End of Charge-Based Memory

3 Resistive Memory Cell Metal (to bit line) Metal (to sensor line) Use ECP, not ECC, for Hard Failures in Resistive Memories Stuart Schechter Gabriel Loh Karin Strauss Doug Burger and introducing (in the ape suit)

4 Resistive Memory Cell Metal (to bit line) Metal (to sensor line)

5 Phase-Change Memory Cell Metal (to bit line) Metal (to sensor line) Phase-Change Memory (PCM)

6 Phase-Change Memory Cell Metal (to bit line) heating element Metal (to sensor line) Phase-Change Memory (PCM)

7 Phase-Change Memory Cell Metal (to bit line) heating element chalcogenide (phase change material) Metal (to sensor line) Phase-Change Memory (PCM)

8 Phase-Change Memory Cell Metal (to bit line) heating element chalcogenide (phase change material) Metal (to sensor line) Phase-Change Memory (PCM)

Phase-Change Memory Cell Metal (to bit line) heating element chalcogenide (phase change material) Metal (to sensor line) Nonvolatile Scalability not impacted by capacitance limits Cells may be written individually Slower, with more energy intensive writes 2x slower for reads, 10x slower for writes Phase-Change Memory vs. DRAM

The heating element loses resistivity, or Expansion/contraction causes detachment – Mean expected lifetime 10 8 writes (but varies) Phase-Change Memory Cell Metal (to bit line) heating element chalcogenide (phase change material) Metal (to sensor line) Hard Failures in Resistive Memories After 10 8 writes together, we’re not connecting like we used to. I just don’t feel the heat anymore.

Phase-Change Memory Cell Metal (to bit line) heating element chalcogenide (phase change material) Metal (to sensor line) DRAM cells encounter soft (transient), errors —May occur between write and future read PCM cells encounter hard (permanent) failures — Occur at write time (detectable by verifying read) — Increase in frequency over product lifetime Phase-Change Memory vs. DRAM

Phase-Change Memory Cell Metal (to bit line) heating element chalcogenide (phase change material) Metal (to sensor line) Living with Hard Failures in Memory Cells Assume we’re already doing these things 1.Accept failure of some fraction of pages — Map failed pages out of logical memory 2.Wear-level data pages/blocks, & within blocks —Shift/rotate data randomly (intervals/locations) 3.Differential writes — Write only cells with values that change 4.Correct errors when possible

Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Error Correction Schemes A Page Must Be Retired When… The first cell within a page fails No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Error Correction Schemes 8 chips 8 bits/chip SEC/SECDED 64 bits 7/8 bits 10.9%/12.5% overhead We use this 12.5% overhead limit for all schemes in our study

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Error Correction Schemes A Page Must Be Retired When… 8 chips 8 bits/chip SEC/SECDED 64 bits 7/8 bits 10.9%/12.5% overhead A block within the page suffers a second error

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 8 chips 8 bits/chip 64 bits Error Correction Schemes Error Correcting Pointers Correction Chip

Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Error Correcting Pointers

Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Error Correcting Pointers

0110 … correction pointer data cells 1 R replacement cell 1 correction entry 1 Full? 1 0 Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 ECP 1

0110 … R 1 0 Full? data cellscorrection entries Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

… R R Full? data cellscorrection entries Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Error Correction Schemes … data cellscorrection entries 1 Full? 4 A row within the page suffers more errors than it has correction entries* No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 A Page Must Be Retired When…

*What if correction entry fails? Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 There’s a precedence rule for that No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

… R R 1 0 Full? data cellscorrection entries Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

… R R Full? 4 data cellscorrection entries Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Error Correction Schemes … data cellscorrection entries 1 Full? 4 A row within the page suffers more errors than it has correction entries* * * No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 A Page Must Be Retired When…

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Error Correction Schemes Wilkerson, Gao, Alameldeen, Chishti, Khellah, & Lu, ISCA 2008 For fixing errors induced by running SRAM caches at low voltages

Error Correction Schemes 0110 … R1 0 R data cellscorrection entries 0001 SEC No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Error Correction Schemes A row within the page suffers more errors than it has correction entries* No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 A Page Must Be Retired When…

8 chips 8 bits/chip Parity Bits 64 bits 8 bits 12.5% overhead Error Correction Schemes Ipek, Condit, Nightingale, Burger, & Moscibroda, ASPLOS 2009 No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Error Correction Schemes Page Byte Paired Page No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Error Correction Schemes Page 160 errors occur within page. (an average of 5 errors per 1024 bits) No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 A Page Must Be Retired When…

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Error Correction Schemes 8 chips 8 bits/chip SEC/SECDED 8 accesses x 64 bits = 512 bit block 8 transfers x 8 bits 64 bits Multiple error correction – 576 bits of storage – 512 data bits – At most 9 corrections possible (Hamming bound)

Error Correction Schemes No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 A 576-bit block (holding 512 data bits) suffers its 10 th error A Page Must Be Retired When…

4kByte (32Kbit) page size 32Byte (512 bit) row size 1 Rank 8 Chips per rank x8 Bit lines per chip 10 8 mean writes until memory cell failure.25 coefficient of variance for cell lifetimes Experimental Parameters

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Half capacity lost on first error (when pages are paired)

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Results No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Results Write Modification Width bit block (16 x 32 bit words) Entire 512 bit region modified (each bit flips with p=0.5)

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code Error Correction Schemes A Review of Hamming Codes Flipping just one data bit changes, on average, half of the hamming code bits

Results Write Modification Width bit block (16 x 32 bit words) 256 bit modification128bit mod

Coefficient of variance = 0.25 Write Modification Width of 512 Bits No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Write Modification Width of 256 Bits No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Write Modification Width of 128 Bits No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Perfect codes would always win if you leveled the wear of the correction bits and data bits Fair Treatment of Perfect Codes

No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9 Coefficient of variance = 0.25 Write Modification Width of 128 Bits Internal Wear Leveling

Coefficient of variance = 0.25 Write Modification Width of 256 Bits Internal Wear Leveling No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Coefficient of variance = 0.25 Write Modification Width of 512 Bits Internal Wear Leveling No correctionPairing 8 SEC 64 ECP 6 Wilkerson 4 Perfect_Code 9

Correction pointers >> Pairing Correction pointers >> SEC over small blocks – Precedence rules >> SEC over correction entries Correction pointers >= MEC over large blocks – Lower computational cost For memory with both hard and transient errors – Use ECP below, on chip (for hard errors) – Use SEC above, off chip (for soft errors) Conclusion

Backup Slide for Responding to Questions You didn’t expect we’d believe this… did you?

56 ? I’m sorry dear, but if that’s the best talk we’ll be capable of even after millions of years of evolution, I think its best we not reproduce.