Manufacturing Process [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al. and presentation by J.Christiansen/CERN]

Fabrication Masks Chips Processed Wafer Processing Wafers

Traditional CMOS Process

A Modern CMOS Process p- p-epi p well n well p+ n+ gate oxide Al (Cu) tungsten SiO2 TiSi2 Dual-Well Trench-Isolated CMOS field oxide dual-well approach uses both n- and p- wells grown on top of a epitaxial layer(using trench isolation areas of SiO2) Epi-layer is a high quality crystal grown on the polished surface of pre-doped silicon wafers for making CMOS nano devices.

Photo-Lithographic Process optical oxidation mask photoresist photoresist coating removal (ashing) stepper exposure Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development acid etch process spin, rinse, dry step

Growing the Silicon Ingot Base material is a single-crystalline, lightly doped wafer between 4 and 12 inches and a thickness of, at most, 1 mm – obtained from cutting a single-crystal ingot into thin slices. Starting wafer of p- type around 2 x 10**21 impurities/m**3. The surface is then doped more heavily with a single crystal epitaxial layer grown over the surface before the wafer goes to the processing company. Important metric – defect density From Smithsonian, 2000

E-Beam Lithography As the miniaturization of IC devices continues, electron beam exposure technology is gaining prominence as a technology for next-generation design rules From: ADVANTEST CORPORATION

Silicon Oxidation The oxide is grown by exposing the silicon surface to high temperature steam. As the oxide grows, the silicon is consumed. The arrows represent the direction of motion of each surface of the oxide. Underneath the nitride mask, the growth is suppressed, and these areas will become the active transistor area. Source: Bell Laboratories

Patterning - Photolithography mask SiO2 PR UV light Oxidation Photoresist (PR) coating Stepper exposure Photoresist development and bake Acid etching Unexposed (negative PR) Exposed (positive PR) Spin, rinse, and dry Processing step Ion implantation Plasma etching Metal deposition Photoresist removal (ashing) Same sequence patterns the complete surface of the wafer. Hence it is a very parallel process transferring hundreds of millions of patterns to the wafer surface simultaneously making cheap manufacturing of complex circuits possible. 1 – deposit thin layer of SiO2 by exposing it to a mixture of high-purity oxygen and hydrogen at 1000C 2 – light-sensitive polymer evenly applied while spinning the wafer to a thickness of 1 micron; polymers cross-link when exposed to light making the affected region insoluble (negative PR) or original insoluable, soluable after exposure (positive PR). COST OF MASKS IS INCREASING QUITE RAPIDLY WITH SCALING OF TECHNOLOGY – A REDUCTION OF MASKS IS OF HIGH PRIORITY! 3 – glass mask containing patter brought in close proximity to the wafer. Mask is transparent in regions we want to process and opaque elsewhere (positive PR). Combination exposed to UV light. Where mask is transparent, photoresist becomes soluable. Dimensions of features is approaching the wavelength of optical light sources (we’re good up to 0.1 micron). Will eventually move to X-ray or electron-beam (much less cost effective). 4 – Exposed photoresist is removed in a acid or base wash, then wafer is “soft-baked” to harden remaining PR 5 – Exposed material (SiO2) is removed via acid, base, and caustic solution wash. 6 – SRD – number of dust particles per cubic foot of air in clean room ranges between 1 and 10 8 – high-temperature plasma is used to selectively remove the remaining photoresist

CMOS Process at a Glance One full photolithography sequence per layer (mask) Built (roughly) from the bottom up 5 metal 2 4 metal 1 2 polysilicon 3 source and drain diffusions 1 tubs (aka wells, active areas) Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers exception!

Example of Patterning of SiO2 Si-substrate Silicon base material 3. Stepper exposure UV-light Patterned optical mask Exposed resist 1&2. After oxidation and deposition of negative photoresist Photoresist SiO2 8. Final result after removal of resist 5. After etching Hardened resist SiO 2 4. After development and etching of resist, chemical or plasma etch of SiO2 Chemical or plasma etch

Diffusion and Ion Implantation Area to be doped is exposed (photolithography) Diffusion or Ion implantation Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform.

Ion Implantation Dopant atoms are ionized and then accelerated by an electric field until they impinge on the silicon surface, where they embed themselves. A polysilicon line crosses the active area in the upper left and forms the gate of a transistor. Needed for well, source and drain regions, doping of polysilicon, adjustment of thresholds Diffusion – wafer placed in quartz tube embedded in a furnace (900 to 1100 C). Gas containing dopant is introduced in the tub. Dopands diffused into the exposed surface both vertically and horizontally. Final dopant concentration is highest at surface and decreases in a gaussian profile deeper in the material Ion implantation – Dopants are introduced as ions into the material by sweeping a beam of purified ions over the surface - acceleration determines how deep ions will penetrate and the beam current and exposure time determine dosage. Independent control of depth and dosage – ion implantation has largely displaced diffusion. However, has a side effect of causing lattice damage to substrate, so usually follow with an annealing step (wafer heated to 1000C for 15 to 30 minutes and allowed to cool slowly). Heating vibrates atoms and allows the bonds to reform. Source: Bell Laboratories

Deposition and Etching Pattern masking (photolithography) Deposit material over entire wafer CVD (Si3N4) chemical deposition (polysilicon) sputtering (Al) Etch away unwanted material wet etching dry (plasma) etching Needed for insulating SiO2, silicon nitride (sacrificial buffer), polysilicon, metal interconnect CVD – chemical vapor deposition uses a gas-phase reaction with energy supplied by heat at around 850C. Use for, eg, silicon nitride Chemical deposition – used for polysilicon. flow silane gas over the heated wafer (coated with SiO2) at approx. 650C. Resulting reaction produces a non-crystaline material – polysilicon. Followed by an implant step to increase its conductivity. Sputtering – used for aluminum. Al evaporated in a vacuum, heat for evaporation delivered by e-bam bombarding. Etching is then used to selectively form patterns (wires, contact holes). Wet etching using acid or basic solutions – hydrofluoric acid buffered with fluoride is used to etch SiO2. Plasma etching becoming more common. Use plasma molecules in heated chamber to “sandblast” the surface. Gives well-defined directionality to the etching action, creating patterns with sharp vertical contours.

Metallization First an insulating glass layer is deposited to cover the silicon, then contact holes are cut into the glass layer down to the silicon. Metal is deposited on top of the glass, connecting to the devices through the contact holes. The graphic shows a snapshot during the filling of a contact hole with aluminum. Needed for insulating SiO2, silicon nitride (sacrificial buffer), polysilicon, metal interconnect CVD – chemical vapor deposition uses a gas-phase reaction with energy supplied by heat at around 850C. Use for, eg, silicon nitride Chemical deposition – used for polysilicon. flow silane gas over the heated wafer (coated with SiO2) at approx. 650C. Resulting reaction produces a non-crystaline material – polysilicon. Followed by an implant step to increase its conductivity. Sputtering – used for aluminum. Al evaporated in a vacuum, heat for evaporation delivered by e-bam bombarding. Etching is then used to selectively form patterns (wires, contact holes). Wet etching using acid or basic solutions – hydrofluoric acid buffered with fluoride is used to etch SiO2. Plasma etching becoming more common. Use plasma molecules in heated chamber to “sandblast” the surface. Gives well-defined directionality to the etching action, creating patterns with sharp vertical contours. Source: Bell Laboratories

F5112 E-Beam Lithography Single-Column System Minimum Feature Size: 100nm Overlay Accuracy: |mean|+3 sigma<=40nm 3 sigma<=15nm Block Exposure Method: Max. No. of Block Patterns: 70

Planarization: Polishing the Wafers Essential to keep the surface of the wafer approximately flat between processing steps. Chemical-mechanical planarization (CMP) step is included before the deposition of an extra metal layer on top of SiO2. The process uses a slurry compound – a liquid carrier with a suspended abrasive component such as aluminum oxide or silica – to microscopicall plane a device layer and to reduce step heights. From Smithsonian, 2000

Self-Aligned Gates Create thin oxide in the “active” regions, thick elsewhere Deposit polysilicon Etch thin oxide from active region (poly acts as a mask for the diffusion) Implant dopant Polysilicon gate is patterned before source and drain are created – thereby actually defining the precise location of the channel region and the locations of the source and drain regions. This allows for very precise positioning of the source and drain relative to the gate. Note that can’t completely stop lateral diffusion – accounts for difference between drawn transistor dimensions and actual ones

Simplified CMOS Inverter P-well Process cut line p well n type substrate - p well/tub

P-Well Mask After p-well use implants to adjust VTn

Active Mask Grown thick oxide. Then use active mask to create thin oxide layers over the active areas – where we are going to place the transistors (source, gate, and drain areas)

Poly Mask First used chemical deposition to deposit polysilicon on wafer. Note thin oxide area for gate oxide - critical (helps determine Vth) doe 0.25 micron technology -> 6.5 to 5.5 microns thick

P+ Select Mask Followed by diffusion (ion implant) to build pfets source and drain areas

N+ Select Mask Followed by diffusion (ion implant) to build nfets source and drain areas

Contact Mask After deposition of SiO2 insulator, then contact holes are etched (in this case to make contacts to source and drain regions)

Metal Mask 62 processing steps for a double/twin tub CMOS process!! tanqueray.eecs.berkeley.edu/~ehab/inv.html

VLSI Fabrication: The Cycle

CMOS N-well Process (cont’d) The n-well CMOS process starts with a moderately doped (impurity concentration less than 1015 cm-3) p-type silicon substrate. Then, an oxide layer is grown on the entire surface. The first lithographic mask defines the n-well region. Donor atoms, usually phosphorus, are implanted through this window in the oxide. This defines, the active areas of the nMOS and pMOS transistors. Thin gate oxide is grown on top of the active regions. The thickness and the quality of the gate oxide are critical fabrication parameters, since they affect the characteristics of the MOS transistor, and its reliability.

CMOS N-well Process (cont’d) The polysilicon layer is deposited using chemical vapor deposition (CVD) and patterned by dry (plasma) etching. The created polysilicon lines will function as the gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the polysilicon gates act as self-aligned masks for the source and drain implantations that follow this step.

CMOS N-well Process (cont’d) Using a set of two masks, the n+ and p+ regions are implanted into the substrate and into the n- well, respectively. The ohmic contacts to the substrate and to the n-well are implanted in this process step.

CMOS N-well Process (cont’d) An insulating silicon dioxide layer is deposited over the entire wafer using CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon contact windows.

CMOS N-well Process (cont’d) Metal is deposited over the entire chip surface using metal evaporation, and the metal lines are patterned through etching. Since the wafer surface is non-planar, the quality and the integrity of the metal lines created in this step are very critical and are essential for circuit reliability.

CMOS N-well Process (cont’d) The composite layout and the resulting cross-sectional view of the chip, showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal interconnections. The final step is to deposit the passivation layer (overglass -for protection) over the chip, except for wire-bonding pad areas.

Advanced Metallization

From Design to Reality…

Design Rules

CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) Color Representation Yellow Green Red Blue Magenta Black Select (p+,n+)

Layers in 0.25 mm CMOS process

Design Rules Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers

3D Perspective Polysilicon Aluminum

Why Have Design Rules? To be able to tolerate some level of fabrication errors such as Mask misalignment Dust Process parameters (e.g., lateral diffusion) Rough surfaces Motivation for design rules – next slide

Intra-Layer Design Rule Origins Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab why would the spacing of the active (n) area be different that drawn? - due to lateral diffusion 0.3 micron 0.15

Inter-Layer Design Rule Origins Transistor rules – transistor formed by overlap of active and poly layers Transistors Catastrophic error Unrelated Poly & Diffusion Thinner diffusion, but still working

Inter-Layer Design Rule Origins, Con’t Contact and via rules M1 contact to p-diffusion M1 contact to poly Mx contact to My Contact Mask Via Masks 0.3 0.14 both materials mask misaligned M1 contact to n-diffusion Contact: 0.44 x 0.44 Note that the minimum area of a contact is 0.44 x 0.44 which is larger than the dimensions of a minimum size transistor!! Excessive changes between interconnect layers are thus to be avoided.

Intra-Layer Design Rules Metal2 4 3

Transistor Layout

Vias and Contacts

Select Layer

IC Layout

CMOS Inverter Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

CMOS Inverter max Layout VDD GND NMOS (2/.24 = 8/1) PMOS (4/.24 = 16/1) metal2 metal1 polysilicon In Out metal1-poly via metal2-metal1 via metal1-diff via pfet nfet pdif ndif

Layout Editor

Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

CMOS Inverters Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m =2l

Layout Design Rule Violation Well-well spacing = 9 M1- M1 spacing = 3 M1width = 4 Active to well edge = 5 Min active width = 3 Poly overlap of active = 2 M2 - M2 spacing = 4 All distances in l this is a test

Building an Inverter A VCC VSS Output Step 1 Step 2 P N P diffusion N diffusion Step 3 Step 4 With permission of William Bradbury

Building a 2 Input NOR Gate Out Step 1 Step 2 Step 3 Step 4 P Sha r ed node Ou t p u VCC Output VCC P Output Shared node A B N VS S Ou t p u VS S VS S N A B A B A B A B With permission of William Bradbury

Building a 2 Input NAND Gate Step 1 Step 3 Output Ou t p u Sha r ed node VS S VCC Step 2 P N Step 4 V Shared node Out With permission of William Bradbury

Combining Logic Functions A Out B B ’ P N VCC VSS With permission of William Bradbury

Cell Symbol to Logic to Transistor Schematic to Layout INPUT OUTPUT LD LD’ SRAM SRAM BIT TRANSISTOR SCHEMATIC OUTPUT LD P2, 1.8 P4, 2.0 INPUT B P1, 1.4 N1, 1.4 A LD’ N2, 2.0 N4, 2.0 OUTPUT P 1.4 N 1.4 LD LD’ P 1.8 N 2.0 P 2.0 P .5/1.0 N .6/1.0 INPUT B A SRAM BIT LOGIC P3, .5/1.0 N3 , .6/1.0 Note the listing of the “L” dimension which is not the minimum defined by the process Minimum poly width “L” = 0.20 With permission of William Bradbury

Schematic to Transistor INPUT LD P1 VCC B P2 OUTPUT P4 P3 LD’ N1 VSS N2 N4 N3 With permission of William Bradbury

Assembling the Transistors by Type and Node Name VCC A INPUT LD B OUTPUT VSS A LD’ B OUTPUT INPUT With permission of William Bradbury With permission of William Bradbury

Connecting the Nodes With permission of William Bradbury LD VCC VSS B OUTPUT INPUT VCC LD

Connecting the Dotes A VCC B B OUTPUT LD INPUT VCC A VCC A B UNMERGED DATA: B INPUT A INPUT VSS OUTPUT VSS A A Notice the addition of contacts where necessary and also the use of redundant contacts to improve reliability LD’ B VSS B With permission of William Bradbury

Cleaning Connections and Completing the layout . P-TAP VCC B A OUTPUT VSS INPUT LD’ P-IMPLANT N-TAP N-WELL P1 P2 P3 P4 N1 N3 N4 N-IMPLANT N2 LDDD Added: Taps Implants Cell boundry With permission of William Bradbury

Using sticks B A B’ VSS VCC Output N diffusion Metal1 P diffusion . B A B’ VSS VCC Output N diffusion Metal1 P diffusion Contact Poly With permission of William Bradbury

Same cell, different shape . . B A B’ VSS VCC Output A B’ B VSS VCC Out With permission of William Bradbury

Cells Designed for Sharing . . 1 Bit Memory Row 1 Compare Row 1 Reference Voltage Sense Ckt. for One Row Height of 1 Memory Bit 1 Bit Memory Row 1 Compare Row 1 Reference Voltage Dual Sense Amp Cell Height Compare Row 2 Memory Row 2 Dual Sense Amps Dual Write Line Ckts Courtesy Mentor Graphics Corp. Layout created using IC-Station. With permission of William Bradbury

Cells Designed for Sharing . . With permission of William Bradbury

Packaging

Packaging Requirements Desired package properties Electrical: Low parasitics Mechanical: Reliable and robust Thermal: Efficient heat removal Economical: Cheap Wire bonding Only periphery of chip available for IO connections Mechanical bonding of one pin at a time (sequential) Cooling from back of chip High inductance (~1nH) More about packaging: http://www.embeddedlinks.com/chipdir/package.htm

Chip to package connection Flip-chip Whole chip area available for IO connections Automatic alignment One step process (parallel) Cooling via balls (front) and back if required Thermal matching between chip and substrate required Low inductance (~0.1nH)

Bonding Techniques

Tape-Automated Bonding (TAB)

New package types BGA (Ball Grid Array) CSP (Chip scale Packaging) Small solder balls to connect to board small High pin count Cheap Low inductance CSP (Chip scale Packaging) Similar to BGA Very small packages Package inductance: 1 - 5 nH

Flip-Chip Bonding

Package-to-Board Interconnect

Package Types Through-hole vs. surface mount From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame Metal pads on 100 – 200 mm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Advanced Packages Bond wires contribute parasitic inductance Fancy packages have many signal, power layers Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery Top level metal pads covered with solder balls Chip flips upside down Carefully aligned to package (done blind!) Heated to melt balls Also called C4 (Controlled Collapse Chip Connection) From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Package Parasitics Use many VDD, GND in parallel Inductance, IDD From Adnan Aziz http://www.ece.utexas.edu/~adnan/vlsi-05/

Signal Interface Transfer of IC signals to PCB Package inductance. PCB wire capacitance. L - C resonator circuit generating oscillations. Transmission line effects may generate reflections Cross-talk via mutual inductance L C Package Chip PCB trace L-C Oscillation Z Transmission line reflections R f =1/(2p(LC)1/2) L = 10 nH C = 10 pF f = ~500MHz

Package Parameters

Package Parameters

Package Parameters 2000 Summary of Intel’s Package I/O Lead Electrical Parasitics for Multilayer Packages

Packaging Faults Small Ball Chip Scale Packages (CSP) Open

Packaging Faults CSP Assembly on 6 mil Via in 12 mil pad Void over via structure

Miniaturisation of Electronic Systems Enabling Technologies : SOC High Density Interconnection technologies SIP – “System-in-a-package” From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

The Interconnection gap Improvement in density of standard interconnection and packaging technologies is much slower than the IC trends IC scaling Time Size scaling PCB scaling Advanced PCB Laser via Interconnect Gap From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

The Interconnection gap Requires new high density Interconnect technologies PCB scaling Advanced PCB Size scaling Thin film lithography based Interconnect technology IC scaling Reduced Gap Time From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

SoC has to overcome… Technical Challenges: Business Challenges: Increased System Complexity. Integration of heterogeneous IC technologies. Lack of design and test methodologies. Business Challenges: Long Design and test cycles High risk investment Hence time to market. Solution System-in-a-Package From ECE 407/507 University of Arizona http://www.ece.arizona.edu/mailman/listinfo/ece407

Multi-Chip Modules

Multiple Chip Module (MCM) Increase integration level of system (smaller size) Decrease loading of external signals > higher performance No packaging of individual chips Problems with known good die: Single chip fault coverage: 95% MCM yield with 10 chips: (0.95)10 = 60% Problems with cooling Still expensive

Complete PC in MCM