Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

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Presentation transcript:

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process CMOS Process

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Circuit Under Design This two-inverter circuit (of Figure 3.25 in the text) will be manufactured in a twin-well process.

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Circuit Layout

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Process Flow These slides only present only a couple of snapshots of the manufacturing process for the circuits presented in the textbook. For a complete overview of all 62 steps, please refer to: Credits for these pictures go to Ehab Hakeem, Prof. Andrew Neureuther and the Simpl program.

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Start Material Starting wafer: n-type with doping level = /cm 3 * Cross-sections will be shown along vertical line A-A’ A A’

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (1) Oxidize wafer (2) Deposit silicon nitride (3) Deposit photoresist

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (4) Expose resist using n-well mask

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (5) Develop resist (6) Etch nitride and (7) Grow thick oxide

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process N-well Construction (8) Implant n-dopants (phosphorus) (up to 1.5  m deep)

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process P-well Construction Repeat previous steps

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Grow Gate Oxide  m thin

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Grow Thick Field Oxide Uses Active Area mask Is followed by threshold-adjusting implants 0.9  m thick

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Polysilicon layer

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Source-Drain Implants

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Source-Drain Implants

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Contact-Hole Definition (1) Deposit inter-level dielectric (SiO 2 ) — 0.75  m (2) Define contact opening using contact mask

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Aluminum-1 Layer Aluminum evaporated (0.8  m thick) followed by other metal layers and glass

Digital Integrated Circuits © Prentice Hall 1995 Manufacturing Process Advanced Metalization