1 Editing A Power Architect Tree What if a user specifies a specific tree configuration?

Slides:



Advertisements
Similar presentations
WEBENCH Power Designer/Architect
Advertisements

Interference Analysis 2K Newly Improved Features : Imperial & Metric Versions. Imperial & Metric Versions. Verifies known Bushing O.D. & Housing I.D. values.
JustinMind: Dynamic Panels
Linear Technology Corporation
Decision Analysis Tools in Excel
An End-User Perspective On Using NatQuery Extraction From two Files T
The World Leader in High Performance Signal Processing Solutions New SOT supervisors.
Interference Analysis 2K Newly Improved Features :  Imperial & Metric Versions.  Verifies known Bushing O.D. & Housing I.D. values thus providing added.
Leveraging Software to Enhance Timing Analysis for Actel RTAX-S Devices Johnny Chung Corporate Applications Engineering Actel Corporation MAPLD 2005.
XPower for CoolRunner™-II CPLDs
Powering CoolRunner™ -II CPLDs. Quick Start Training Agenda Regulator Overview – Linear vs. Switching – Linear Regulators – Switching Regulators CoolRunner-II.
Concepts of Database Management Seventh Edition
Viewing this Tutorial Use the ‘Down’ arrow on your keyboard, or left click your mouse, to move to the next point. Use the ‘Up’ arrow to go back. Use the.
ELECTRICAL. Circuits Outline Power Hub Microcontroller Sensor Inputs Motor Driver.
Integrated Circuits Laboratory Faculty of Engineering Digital Design Flow Using Mentor Graphics Tools Presented by: Sameh Assem Ibrahim 16-October-2003.
PYRO-STAG De-Icer Optimizer Controller Technical presentation 2013.
TOP, The Output Processor TOP, The Output Processor  Training Presentation Electrotek Concepts.
© 2012 Pearson Education. Upper Saddle River, NJ, All rights reserved. Electronic Devices, 9th edition Thomas L. Floyd Electronic Devices Ninth.
Embedded Systems Power Supply. Consideration Voltage – Output voltage – In put voltage Current Ripple Power Consumption Isolation Interference Protection.
IC Voltage Regulator.
Power Electronics and Drives (Version ) Dr. Zainal Salam, UTM-JB 1 Chapter 3 DC to DC CONVERTER (CHOPPER) General Buck converter Boost converter.
Dataface API Essentials Steve Hannah Web Lite Solutions Corp.
Applied Harmonics Control of Harmonics
© 2012 MISTRAS GROUP, INC. ALL RIGHTS RESERVED. DISSEMINATION, UNAUTHORIZED USE AND/OR DUPLICATION NOT PERMITTED. TankReporter 2.0 A Step by Step Example.
Copyright © 2007, Oracle. All rights reserved. Managing Concurrent Requests.
XPower for CoolRunner™ XPLA3 CPLDs. Quick Start Training Overview Design power considerations Power consumption basics of CMOS devices Calculating power.
1 Introduction to Xilinx ISL8.1i & 11.1 Schematic Capture 1.
Tools - Implementation Options - Chapter15 slide 1 FPGA Tools Course Implementation Options.
FPGA_Editor Probes. . Probe Overview 2 Adding a Probe : GUI Probes tie an internal signal to an output pin To Launch the GUI: Click the “probes” button.
An Introduction to Designing and Executing Workflows with Taverna Aleksandra Pawlik materials by: Katy Wolstencroft University of Manchester.
LDO or Switcher? …That is the Question Choosing between an LDO or DC/DC Converter Frank De Stasi Texas Instruments.
Derek Snow 6/13/2009.  What is Form?  Creating Forms  Form Views  Calculated Controls.
XP. Objectives Sort data and filter data Summarize an Excel table Insert subtotals into a range of data Outline buttons to show or hide details Create.
WEBENCH Schematic Editor Hands On Problems
Common mistakes Please don’t take offense if examples are taken from your report.
Backchannel Issues Walter Katz Signal Integrity Software, Inc. IBIS-ATM April 8, 2014.
1 Software Reliability Analysis Tools Joel Henry, Ph.D. University of Montana.
1 Lesson 18 Managing and Reporting Database Information Computer Literacy BASICS: A Comprehensive Guide to IC 3, 3 rd Edition Morrison / Wells.
With Microsoft Excel 2007Comprehensive 1e© 2008 Pearson Prentice Hall1 Chapter 4: PowerPoint Presentation GO! with Microsoft Excel ® 2007 Comprehensive.
Testability Analysis Last revised 08/11/2005. Introduction Leverage the existing FMECA data Define and Edit Detection/Isolation Groups Define and Edit.
 General description of Power Supply  Advantages/Disadvantages of SMPS  Block diagram of SMPS  Basic topologies and practical  Requirements  Various.
WEBENCH ® Power Designer Howard Chen Applications Engineer March 22, 2016.
Introduction to Linear Voltage Regulators Krishna Kishore Reddy K 2010H223084H.
Chapter 6: Voltage Regulator
Rectifiers, Filters and Regulator
WEBENCH® Coil Designer
Dept. of Electrical and Computer Engineering Michigan State University
Prepared by(Group no. 3):
Lesson 23 Managing and Reporting Database Information
Dept. of Electrical and Computer Engineering
M1.5 Foundation Tools Xilinx XC9500/XL CPLD
Amplifier Designer Stealth Release.
THE PROCESS OF EMBEDDED SYSTEM DEVELOPMENT
Microsoft Word Illustrated
Programmable Logic Controllers (PLCs) An Overview.
Introduction to Linear Voltage Regulators
Presenter: Ujjwal Karki, PhD Candidate, PE Lab, MSU
AUTOTRANSFORMERS.
Chapter 6: Voltage Regulator
BLOCK DIAGRAM: Micro controller.
ChipScope Pro Software
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
Microsoft Excel 101.
LM2596: Buck Regulator, Switching, 3.0 A
Data Acquisition (DAQ)
Access: Queries II Participation Project
Instructional presentation
ChipScope Pro Software
easYgen-3000XT Series Training
POWER ELECTRONICS DC-DC CONVERTERS (CHOPPERS) PART 1
Presentation transcript:

1 Editing A Power Architect Tree What if a user specifies a specific tree configuration?

222 WEBENCH Power Designer WEBENCH Visualizer The WEBENCH Tool Suite Power Architect, FPGA /Processor and System Power Architect

333 Design This Power Supply In Seconds? Many Loads, Many Supplies Core Supply FPGA IO CCD Motor 9 Loads and 5 Voltages

WEBENCH® FPGA Power Architect Add FPGA Select Device From List Configure Loads 4

FPGA Issues The output current is a nominal value –Users should use vendor supplied current calculators to verify the actual current used for the specific application/utilization 5

66 Enter Additional Loads 6 Voltage, Current, and Special Requirements Included For: Max Voltage Ripple Isolated Supplies Soft Start Post Supply Filters LDO Preferred Add All Of Your Own Additional System Loads Next

77 Sequencing Requirements 7 Sequencing requirements of the selected FPGA/uP captured Modify sequencing based on system requirement Devices with Enable pin are selected to meet sequencing requirements Rails with same output voltage but different sequencing requirements are separated to satisfy sequencing requirements 1) Click to see sequencing diagram

888 Each Architecture Is Tuned With The WEBENCH Optimizer, Now For Systems Optimizer Dial System Efficiency 94%76% Size Relative System Cost

WEBENCH FPGA Power Architect Selects The Best Solutions For Every Rail Intermediate Rail (12V) Supply 2 (1.25V) Supply 4 (1.8V) Supply 3 (3.3V) Supply 5 (2.5V) Loads 9

10 Presenting The User With The Intermediate Rail Options And Performance Trade-Offs Intermediate Rail Options Can Be Reviewed & Compared Quickly 23V 3V No I-Rail 12V 5V 12V Smallest Footprint Highest Efficiency Lowest Cost 12V 5V

Desired Power Tree 11 12V 12V, 7.5A 5V, 2.4A 3.3V,.8A 2.5V,.13A LDO 1.9V, 1.9A 1.8V, 1A 1.5V, 1.3A 1.2V,.8A 1V, 1.8A 3.3V

Enter loads 12 Enter all loads except for the unregulated 12V, 7.5A load. Only used 1 input source.

Select Architecture 13 Architecture 301 has 5V and 3.3V intermediate rails. This is close to what is in the spec.

Select Alternate Regulator 14 2) Select alternate regulator if desired 1) Click to select a regulator postion

Edit the block diagram 15 Click on the Edit button

Move Supplies 16 1) Click on the supply that you want to move 2) Click on the "Move" drop down to specify move to supply 4

Move Remaining Supplies 17 1) Do the same for the remaining supplies 2) Click on the "Move" drop down to specify move to supply 4

Move 1V Supply to Source 18 1) Select the 1V supply 2) Click on the "Move" drop down to specify move to Source_DC_1

Save Changes 19 Click Save Changes button

Compare to Other Architectures 20 Click Compare button

Compare to Other Architectures 21 New architecture is higher efficiency, but higher cost and larger footprint. OldNew 83.4%86.8% $13.21$ mm 2 Original New

Create Project 22 Click Create Project button

WEBENCH Project 23 Project designs have now been created and can be manipulated in WEBENCH Designer.