ETE 204 - Digital Electronics Flip-Flops and Registers [Lecture:13] Instructor: Sajib Roy Lecturer, ETE, ULAB

Flip-Flops (continued) Summer 2012 ETE 204 - Digital Electronics 2

SR Flip-Flop - Clock (Ck) --- denoted by the small arrowhead ● The SR Flip-Flop has three inputs - Clock (Ck) --- denoted by the small arrowhead - Set (S) and Reset (R) ● Similar to an SR Latch - S = 1 sets the flip-flop (Q+ = 1) - R = 1 resets the flip-flop (Q+ = 0) ● Like the D Flip-Flop, the Q output of an SR Flip-Flop only changes in response to an active clock edge. - Positive edge-triggered - Negative edge-triggered Summer 2012 ETE 204 - Digital Electronics 3

} } } SR Flip-Flop Q+ = Q Q+ = 0 Q+ = 1 State change occurs 0 0 0 0 } } } Q+ = Q 0 0 1 1 store 0 1 0 0 Q+ = 0 positive edge-triggered SR Flip-Flop 0 1 1 0 reset 1 0 1 0 0 1 1 1 Q+ = 1 set 1 1 not 1 1 1 allowed State change occurs after active Clock edge Summer 2012 ETE 204 - Digital Electronics 4

SR Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock Summer 2012 ETE 204 - Digital Electronics 5

SR Flip-Flop: Timing Diagram Summer 2012 ETE 204 - Digital Electronics 6

JK Flip-Flop ● The JK Flip-Flop has three inputs - Clock (Ck) --- denoted by the small arrowhead - J and K ● Similar to the SR Flip-Flop - J corresponds to S: J = 1 → Q+ = 1 – K corresponds to R: K = 1 → Q+ = 0 ● Different from the SR Flip-Flop in that the input combination J = 1, K = 1 is allowed. - J = K = 1 causes the Q output to toggle after an active clock edge. Summer 2012 ETE 204 - Digital Electronics 7

} } } } JK Flip-Flop Q+ = J.Q' + K'.Q Q+ = Q Q+ = 0 Q+ = 1 Q+ = Q' store Q+ = 0 reset Q+ = 1 set Characteristic Equation: Q+ = J.Q' + K'.Q Q+ = Q' toggle Summer 2012 ETE 204 - Digital Electronics 8

JK Flip-Flop (master-slave) SR Latches Enabled on opposite levels of the clock Summer 2012 ETE 204 - Digital Electronics 9

JK Flip-Flop: Timing Diagram Summer 2012 ETE 204 - Digital Electronics 10

T Flip-Flop - Clock (Ck) --- denoted by the small arrowhead ● The Toggle (T) Flip-Flop has two inputs - Clock (Ck) --- denoted by the small arrowhead - Toggle (T) ● The T input controls the state change - when T = 0, the state does not change (Q+ = Q) - when T = 1, the state changes following an active clock edge (Q + = Q') ● T Flip-Flops are often used in the design of counters. Summer 2012 ETE 204 - Digital Electronics 11

T Flip-Flop Characteristic Equation: Q+ = T.Q' + T'.Q = T xor Q Summer 2012 ETE 204 - Digital Electronics 12

T Flip-Flop: Timing Diagram Summer 2012 ETE 204 - Digital Electronics 13

Building a T Flip-Flop Summer 2012 ETE 204 - Digital Electronics 14

Asynchronous Control Signals Summer 2012 ETE 204 - Digital Electronics 15

Asynchronous Control Signals: Timing Diagram Summer 2012 ETE 204 - Digital Electronics 16

D FF with Clock Enable Summer 2012 ETE 204 - Digital Electronics 17

Registers Summer 2012 ETE 204 - Digital Electronics 18

Registers Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, a register with n D flip-flops can store n bits of information. A load signal can be ANDed with the clock to enable and disable loading the registers. A better approach is to use registers with clock enables if they are available. Summer 2012 ETE 204 - Digital Electronics 19

Register: 4 bits Summer 2012 ETE 204 - Digital Electronics 20

Data Transfer between Registers ● Data transfer between registers is a common operation in computer (i.e. digital) systems. ● Multiple registers can be interconnected using tri-state buffers. ● Data can be transferred between two registers by enabling the proper tri-state buffer. Summer 2012 ETE 204 - Digital Electronics 21

Data Transfer between Registers Summer 2012 ETE 204 - Digital Electronics 22

Register with Tri-state Output Summer 2012 ETE 204 - Digital Electronics 23

Data Transfer using Tri-state Bus Summer 2012 ETE 204 - Digital Electronics 24

Shift Register A shift register is a register in which binary data can be stored and shifted either left or right. The data is shifted according to the applied shift signal; often there is a left shift signal and a right shift signal. A shift register must be constructed using flip-flops (i.e. edge- triggered devices); it cannot be constructed using latches or gated-latches (i.e. level-sensitive devices). Summer 2012 ETE 204 - Digital Electronics 25

Shift Register: 4 bits Summer 2012 ETE 204 - Digital Electronics 26

Shift Register (4 bits): Timing Diagram Summer 2012 ETE 204 - Digital Electronics 27

8-bit SI SO Shift Register Summer 2012 ETE 204 - Digital Electronics 28

4-bit PIPO Shift Register Summer 2012 ETE 204 - Digital Electronics 29

4-bit PI PO Shift Register: Operation Summer 2012 ETE 204 - Digital Electronics 30

Parallel Adder with Accumulator Summer 2012 ETE 204 - Digital Electronics 31

Parallel Adder with Accumulator In computer circuits, it is frequently desirable to store one number in a register (called an accumulator) and add a second number to it, leaving the result stored in the register. Summer 2012 ETE 204 - Digital Electronics 32

n-bit Parallel Adder with Accumulator Summer 2012 ETE 204 - Digital Electronics 33

Loading the Accumulator Before addition in the previous circuit can take place, the accumulator must be loaded with X. This can be accomplished in several ways. The easiest way is to first clear the accumulator using the asynchronous clear inputs on the flip-flops, and then put the X data on the Y inputs to the adder and add the accumulator in the normal way. Alternatively, we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator. Summer 2012 ETE 204 - Digital Electronics 34

Adder Cell with Multiplexer Summer 2012 ETE 204 - Digital Electronics 35

Questions? Summer 2012 ETE 204 - Digital Electronics 36