Test #2 Combinational Circuits – MUX Sequential Circuits – Latches – Flip-flops – Clocked Sequential Circuits – Registers/Shift Register – Counters – Memory

Multiplexer 2-to-1 mux 4-to-1 mux

2-to-1 mux A 2-input mux is controlled by a single control line s. If s=0, y=a and y=b if s=1.

Implementation

4-to-1 Mux

(Creating a 4 x 1 MUX from 2 x 1 MUX)

Latches Latches are level sensitive. Latches propagate values from input to output continuously. S sets Q =1; R sets Q=0 – Active low inputs are enabled by 0s. – Active high inputs are enabled by 1s.

SR Latch with NOR Gates t PDSQ =2 NOR gate delays. t PDRQ_ =1 NOR gate delay Forbidden State SR are trigger pulses which can return to zero once Q is set. Active High inputs

Typical Mode of Operation 1.Both inputs of the latch remain at 0 unless the state has to be changed. 2.When both S and R are equal to 0, the latch can be in either the set or the reset, depending on which input was most recently a 1. S must go back to 0 in order to avoid S=R=1. Q and Q’ do not change states when S goes back to 0. R must go back to 0 in order to avoid S=R=1. Q and Q’ do not change states when R goes back to 0.

SR Latch with NAND Gates 1.Both inputs of the latch remain at 1 unless the state has to be changed. 2.When both S and R are equal to 1, the latch can be in either the set or the reset, depending on which input was most recently a 1. R must go back to 1 in order to avoid S=R=0. Q and Q’ do not change states when R goes back to 1. S must go back to 1 in order to avoid S=R=0. Q and Q’ do not change states when S goes back to 1.

Comparison (activated with a 1) (activated with a 0)

SR Latch with NAND Gates Active low inputs

SR latch with Control Line (En=0) 1. En=0, Q and Q’ will not be changed! 0 1 1

SR latch with Control Line (En=1) 1.En=1, Q and Q’ will be affected by S and R. 2.We now have active-high enabled circuit! 1 S’ R’

D Latch

D Latch (En=0) 0 1 1

D Latch (En=1) 1 D’ D Q follows D as long as En is asserted (En=1). Data is temporary stored when En is 0.

D-latch Operation

D-Latch (CK=0) 0 D DB 0 0

D-Latch (CK=1) 1 D DB D D

Analyze D Latch Using Boolean Algebra

D Flip-Flop

Negative Edge triggered D Flip-Flop Clk=0 0 1 Q=Y hold

Negative Edge triggered D Flip-Flop Clk=1 1 0 Y=D hold

Negative Edge Triggered D Flip- Flop CK of latch 1 CK of latch 2 OUT=X Y=D 2: Hold 1: Track 1:hold 2:track 1 2 1:hold 2:track Q=Y Not enough time for D→Y →Q Q will hold steady The value that is produced at the output of the flip-flop is the value that was stored in master stage immediately before the negative edge Occurred.

Positive Edge D-Flop 1 2 CK of latch 2 CK of latch 1 X X=IN OUT=X 1: Hold 2: Track 2:hold 1:track 2:hold 1:track

D-Type Positive Edge Triggered Flip-Flop (CLK=0) CLK =0, maintain the present state

D-Type Positive Edge Triggered Flip-Flop 0 0→ → 0 Q changes D=0 as Clk=0→ 1

D-Type Positive Edge Triggered Flip-Flop 1 0→ 1 1 → 0 1 → 1 Q changes D=1 as Clk=0→ 1

D-Type Positive Edge Triggered Flip-Flop 0 → 1 1 S The flip-flop is unresponsive to changes in D 1 1 D=0→ 1 as Clk=1 S’ Please explore different possible value of S on your own. This will work even for S=R=1 and S=R=0.

Symbol of D Flip-Flops

Analysis of Clocked Sequential Circuits

Example of a Sequential Circuit D flip-flops

Example: Start with A=0, B=0, x=0. A(next)=0 B(next)=0 Y(next)=0

What are A(next), B(next) and y(next) given that A=1, B=1 and X=1? D flip-flops

Alternate State Table

State Diagram Each circle is a state When x=1, y=0.

State Diagram Each circle is a state When x=0, y=1.

Detects 0 in the bit stream of data Output is a 0 as long as input is a 1. The first 0 after a string of 1 transfers the circuit back to 00.

Summary

Shift Register

Register A register is a group of flip-flops, each one of which is capable of storing one bit of information. Issues: – You do not have an option hold the output when you don’t want to outputs updated. 4 D flip-flops=4 bits of storage=4-bit register

4-bit Register with Parallel Load Control

Load=“1”→Update “1” “0” “1” “I 0 ” I 0 is fed to DFF when Load is a 1.

Load=“0”→Hold! “0” “1” “A 0 ” “0” “A 0 ” A 0 is fed to DFF when Load is a 0. So the output is holding!

Four Bit Shift Register Q of DFF1 gets SI after the first rising edge of the CLK Q of DFF2 gets SI after the second rising edge of the CLK Q of DFF3 gets SI after the third rising edge of the CLK Q of DFF4 gets SI after the fourth rising edge of the CLK

Block Diagram of a Universal Shift Register This is called the universal shift register because it has both shifts and parallel load capabilities.

Detail Implementation

Four-to-one-line Mux

Mode Control

S0=0, S1=0 [No Change Mode] S0=0, S1=0

S0=1, S1=0 [Shift Right Mode] S1=0, S0=1

S0=0, S1=1 [Shift Left Mode] S1=1, S0=0

S0=1, S1=1 [Parallel Load Mode] S1=1, S0=1

Counter Section 6.3

Types of Counter Binary Ripple Counter Synchronous Counter

Reset Binary Ripple Counter Respond to negative edge of the clock

Reset Binary Ripple Counter D 0 (n+1)=A 0 (n) ’ The first flip-flop always toggles itself A3A2A1A Each D flip-flop is designed to flip Itself. Each D flip-flop is triggered by the output of the previous DFF.

Reset Binary Ripple Counter 0→1 0 →0 1 →0 1 1 → A3A2A1A

Reset Binary Ripple Counter 0→1 → 0 0 →0 →1 0 →0 →0 1 →0 → →1 → →1 →0 A3A2A1A

Reset Binary Ripple Counter Respond to negative edge of the clock Each DFF is triggered by the previous DFF.

Counter as a Frequency Divider DecA3A2A1A Start from 0, advance to 15, go back to 0. A 0 repeats after 2 cycles. A 1 repeats after 4 cycles. A 2 repeats after 8 cycles. A 3 repeats after 16 cycles. So a counter can be used as frequency divider. Reset is used to initialize the output to a 0

Synchronous Counters Synchronous counters are different from ripple counters in that clock pulses are applied to the input of all flip-flops.

Binary Counter

JK Flip-Flop

Binary Counter →1 0 →0 0→1 0 →0

→1 → 0 0 →0 →0 0→1 →0 0 →0 →1 0 →0 →0

Memory Section 7.2

Block Diagram of a Memory Unit

74LS189 RAM [A3,A2,A1,A0]=address inputs [D3,D2,D1,D0]=data inputs [S3,S2,S1,S0]=outputs ME,WE control the direction of transfer VCC=power GND=ground

Logic Diagram memory cell Each word is enabled by the 4-input AND

Write →Read

Logic Diagram memory cell Each word is enabled by the 4-input AND

Switch Characteristics

Switching Time Waveforms 17 nS23 nS -7 nS for address -14 nS for data A negative hold time means that the address/data can change before the rising edge of WE because the there is internal delay through the chip.

Write (ME=0, WE=0) D1 D2 D3 D4 [hi Z ? ]

READ (ME=0, WE=1) Complement of data stored

HOLD (ME=1, WE=X) X 1 0 Hi-Z output