Feb. 25, 19991 How the Rest of Hubble works (some of it, anyway) Computers and Communications.

Slides:



Advertisements
Similar presentations
Computer Architecture
Advertisements

More on Processes Chapter 3. Process image _the physical representation of a process in the OS _an address space consisting of code, data and stack segments.
The ATA/IDE Interface Can we write a character-mode device driver for the hard disk?
In this presentation you will:
Processor System Architecture
FIU Chapter 7: Input/Output Jerome Crooks Panyawat Chiamprasert
Page 1 Aalborg University Communication system for the AAUSAT-II Communication System for the AAUSAT-II Kresten K. Sørensen Department.
Process Description and Control Module 1.0. Major Requirements of an Operating System Interleave the execution of several processes to maximize processor.
11/13/01CS-550 Presentation - Overview of Microsoft disk operating system. 1 An Overview of Microsoft Disk Operating System.
1 Hardware and Software Architecture Chapter 2 n The Intel Processor Architecture n History of PC Memory Usage (Real Mode)
1 Process Description and Control Chapter 3. 2 Process Management—Fundamental task of an OS The OS is responsible for: Allocation of resources to processes.
CS335 Networking & Network Administration Tuesday, May 11, 2010.
Using Two Queues. Using Multiple Queues Suspended Processes Processor is faster than I/O so all processes could be waiting for I/O Processor is faster.
Input/Output and Communication
Group 5 Alain J. Percial Paula A. Ortiz Francis X. Ruiz.
MAVEN CDR May 23-25, 2011 Particles and Fields Package Pre-Environmental Review May , 2012 Flight Software Peter R. Harvey Mars Atmosphere and Volatile.
The University of New Hampshire InterOperability Laboratory Serial ATA (SATA) Protocol Chapter 10 – Transport Layer.
Process Description and Control Chapter 3. Major Requirements of an OS Interleave the execution of several processes to maximize processor utilization.
Topics Introduction Hardware and Software How Computers Store Data
1. 2 Purpose of This Presentation ◆ To explain how spacecraft can be virtualized by using a standard modeling method; ◆ To introduce the basic concept.
ISUAL Instrument Software S. Geller. CDR July, 2001NCKU UCB Tohoku ISUAL Instrument Software S. Geller 2 Topics Presented Software Functions SOH Telemetry.
Engineering Telemetry Hubble Space Telescope Tom Wheeler Chris Long
CHAPTER 3 TOP LEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION
Khaled A. Al-Utaibi  Interrupt-Driven I/O  Hardware Interrupts  Responding to Hardware Interrupts  INTR and NMI  Computing the.
MG 1/10/01 1 PCS SMOV-3B Review Objectives Overview Activity Descriptions Requirements.
Recall: Three I/O Methods Synchronous: Wait for I/O operation to complete. Asynchronous: Post I/O request and switch to other work. DMA (Direct Memory.
IES Flight Software J. Hanley / P. Mokashi May 29, 2013.
The Functions of Operating Systems Interrupts. Learning Objectives Explain how interrupts are used to obtain processor time. Explain how processing of.
Lecture 3 Process Concepts. What is a Process? A process is the dynamic execution context of an executing program. Several processes may run concurrently,
Computer Organization - 1. INPUT PROCESS OUTPUT List different input devices Compare the use of voice recognition as opposed to the entry of data via.
Time Management.  Time management is concerned with OS facilities and services which measure real time, and is essential to the operation of timesharing.
ECE 526 – Network Processing Systems Design Computer Architecture: traditional network processing systems implementation Chapter 4: D. E. Comer.
Operating System 1 COMPUTER SYSTEM OVERVIEW Achmad Arwan, S.Kom.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
Electronic Analog Computer Dr. Amin Danial Asham by.
80386DX functional Block Diagram PIN Description Register set Flags Physical address space Data types.
Process Description and Control Chapter 3. Source Modified slides from Missouri U. of Science and Tech.
CE Operating Systems Lecture 2 Low level hardware support for operating systems.
Lecture 4 Mechanisms & Kernel for NOSs. Mechanisms for Network Operating Systems  Network operating systems provide three basic mechanisms that support.
GLAST Large Area Telescope LAT Flight Software System Checkout TRR Test Suites (Backup) Stanford Linear Accelerator Center Gamma-ray Large Area Space Telescope.
Laboratory 2 Group 19 The Group of Destiny. User Interface - Debugging Objectives:  Display: Sensor data (telemetry) – including IR sensors, status of.
IT3002 Computer Architecture
Memory Management OS Fazal Rehman Shamil. swapping Swapping concept comes in terms of process scheduling. Swapping is basically implemented by Medium.
Different Microprocessors Tamanna Haque Nipa Lecturer Dept. of Computer Science Stamford University Bangladesh.
Tracing the JWST Proposal from User Interface to Commanding of an Instrument Margaret Meixner & WIT Balzano, Robinson & CMD.
1 Process Description and Control Chapter 3. 2 Process A program in execution An instance of a program running on a computer The entity that can be assigned.
COMP091 – Operating Systems 1 Memory Management. Memory Management Terms Physical address –Actual address as seen by memory unit Logical address –Address.
1 Device Controller I/O units typically consist of A mechanical component: the device itself An electronic component: the device controller or adapter.
HarveyFIELDS iCDR – Flight Software Solar Probe Plus FIELDS DCB Flight Software Design Peter Harvey University of California 1.
NICMOS Suspend Event STB 632 “MECH_2_MAX_RETRIES_EXCEEDED” 2008/069.
GLAST Large Area Telescope LAT Flight Software System Checkout TRR FSW Overview Sergio Maldonado FSW Test Team Lead Stanford Linear Accelerator Center.
Chapter 11 System Performance Enhancement. Basic Operation of a Computer l Program is loaded into memory l Instruction is fetched from memory l Operands.
Logic Gates Dr.Ahmed Bayoumi Dr.Shady Elmashad. Objectives  Identify the basic gates and describe the behavior of each  Combine basic gates into circuits.
1 Chapter 1 Basic Structures Of Computers. Computer : Introduction A computer is an electronic machine,devised for performing calculations and controlling.
File-System Management
Chapter 2: System Structures
Network Core and QoS.
Morgan Kaufmann Publishers Computer Organization and Assembly Language
Module 2: Computer-System Structures
Processor Fundamentals
Process Description and Control
Components of a CPU AS Computing - F451.
Module 2: Computer-System Structures
COMP755 Advanced Operating Systems
Network Core and QoS.
Chapter 13: I/O Systems “The two main jobs of a computer are I/O and [CPU] processing. In many cases, the main job is I/O, and the [CPU] processing is.
Presentation transcript:

Feb. 25, How the Rest of Hubble works (some of it, anyway) Computers and Communications

Feb. 25, Summary of on-board computers DF-224/Coprocessor –Executes spacecraft command timeline. Provides pointing control, power system control, gathers telemetry, provides routine safemode protection, and much more NSSC-I –Executes SI command timeline. Provides safety monitoring, special purpose computing, and data interface for SIs. SI computers –SI specific operations, science data formatting and processing, local health and safety monitoring. PSEA –Provides safemode control for HST when DF-224 is down

Feb. 25, DF-224/Coprocessor DF-224 –3 redundant CPUs, only one used at a time Fixed point arithmetic Two’s complement representation of negative numbers –6 Memory Units Each physical memory unit has 8K 24 bit words of plated wire memory Only 4 units may be powered at once (32K words of available memory) Only 2 units are used for code (16K words) –3 redundant internal data busses, 2 redundant external data busses –Programmed in DF assembly language Coprocessor –Provides 8 memory modules (8K 24 bit words) addressable by both the DF and the coprocessor –2 redundant processors, each with a 386 and 1MB RAM (not visible to DF) –Programmed in C

Feb. 25, 19994

5

6 DF-224 & COPROCESSOR BLOCK DIAGRAM 1 MB RAM 64 KB EEPROM KB EEPROM 2 64 KB PROM 256 KB EEPROM 2 64 KB EEPROM 1 64 KB PROM 1 MB RAM 386 Shared Memory 64K Words Power Supply 386 Shared Memory 64K Words Power Supply Co- Processor IDB-A IDB-B DF-224

Feb. 25, DF-224 Flight Software Only two executable images are on-board –Safemode Utility(SMU) is essentially a boot mode memory dump, diagnostics, limited telemetry, software block load, etc. provides no control of HST (only used while PSEA is in control) –Vehicle Support Software (VSS) provides all other functionality Telemetry processing Command timeline execution Pointing control, including various safemodes Other support functions

Feb. 25, DF-224 Flight Software Structure Vehicle Support Software (VSS) is based on the use of 6 processing loops, executing at 6 different rates: 1kHz, 40 Hz, 10 Hz, 1 Hz, 0.1 Hz and 1/300 Hz. Functionality is assigned to a process based on the rate at which the task must be accomplished Each process has an allocated amount of time it can use Interrupt scheme gives high rate processes priority over lower rate processes, but design is such that no process should ever exceed its time allocation Executive checks on the use of time by each process, exceeding allocations will lead to a PSEA safemode entry

Feb. 25, 19999

10

Feb. 25, Telemetry processing Flight software collects data for the engineering telemetry stream 3 Rates are available –500 bps: safing only –4000 bps: original standard –32000 bps: current standard 1 kHz and 40 Hz processes control the collection and output of the data –Operates on one byte quantities –Handles both hardware and software data –Table driven definition of telemetry format allows for changes with time bps format timing –Cycles through byte parameters in 50 msec. (one minor frame) –Processes 4 1-byte parameters each cycle of the 1kHz process –1200 minor frames in a major frame (60 seconds)

Feb. 25, TDM telemetry format Trivial Example More Complicated Example Measures 1200 temperatures each minute Measures 6 voltages every 300 msec. Reports 4 24-bit variables every 200 msec. Reports FGS1 status every 25 msec.

Feb. 25, Command Types Hardware commands –Header + data word(s) –Destination of command is encoded in header –Header identifies type of hardware command Low level discrete (on/off) High level discrete (on/off) Serial data –Serial data commands include one or more data words (16 bits/word) which go to the designated hardware element Software commands –Header indicates which software function the command will go to 64 software commands are available Example: #51 command executes a small angle maneuver –Variable number of data words are included, depending on the function of the command

Feb. 25, Executing Commands Real time commands are sent from the ground for immediate execution –Flight software uses checksum to validate the uplinked data –Executive (40 Hz process) sends command to proper destination, either hardware or software Block loads are sent from the ground to load command data into stored command processors –Each block load contains the address in memory to place the data –Each block load can have up to 63 data words –Checksum on block load is verified before block is stored in memory –Block loads can be designated for any one of three stored command processors –Each stored command has some timing information included with it Stored commands are executed by the stored command processors –Most stored commands are uplinked from the ground and executed once –Some stored commands are procedures (e.g. guide star acquisitions) which are left on-board and reused many times –Some stored commands are permanently resident and used to respond to safemode situations

Feb. 25, General attributes of command processors Each command packet has a time tag associated with it –Absolute execution time (in units of spacecraft clock ticks to one second accuracy) –Delta time after previous command (in units of 1 second) –A few commands implicitly have delta time tags of 0 seconds (immediate execution) Each command processor maintains a pointer to the next command to be executed –Execution time is computed based on type of time tag –Execution time is in units of one second –Processor can be idled by setting address pointer to 0 Executive cycles through each of the processors each 40 Hz. cycle and checks if the current time matches the execution time –If so, executes command by sending to appropriate hardware or software destination –Moves pointer down to the next command and computes its execution time Command pointer for each processor can be moved by command in another processor or by the flight software itself

Feb. 25, DF-224 command processors Timed processor –Contains primary spacecraft timeline (slews, etc.) –Does not support logical constructs, executes sequentially –Pointer can be moved by software and other processes (used for safemode situations) Conditional processor –Supports logical constructs Test for success, wait for completion, time outs, limited do-loop support, etc. Used for guide star acquisitions –Pointer can be moved by software and other processes Used for loss of lock recovery Used for some safemode situations Special processor –Works just like the Timed Processor, used only occasionally for special tests

Feb. 25,

Feb. 25, Physical memoryLogical memory K “Operational” SPC memory Executing here Stored Command Memory management PMU-1 PMU-3 Cop-1 Cop-2 LMU-1 LMU-2 LMU-3 LMU-4 Future Past “temporal discontinuity” Next load

Feb. 25, DF-224 Vehicle control modes

Feb. 25, Additional DF-224 Processing SIC&DH Interface –Communications between DF-224 and NSSC-I is via PITs (Processor Interface Tables) –One table goes each way each half second –SSM PIT tells NSSC-I about DF-224 and spacecraft Safing directions Spacecraft time Take data flag Maneuver request accepted Maneuver information Guide star information –SIC&DH PIT tells DF-224 about SIs Requests V2-V3 offsets Requests STR/SSR start/stop Indicates that a payload safing has been initiated –Protocol indicates to each computer that the other is alive DF-224 safes SIC&DH and SIs if it does not receive PIT NSSC-I safes SIs if it does not receive PIT

Feb. 25, Additional DF-224 Processing Pointing Control –Sensor data processing –Control laws –Outputs torque commands Solar Array rotations High Gain Antenna pointing –Spline commands to reposition HGAs –Tracking uses HST and TDRSS ephemeris and pointing direction of vehicle to automatically track TDRSS Electrical Power System –Battery state of charge and trickle charge calculations (health and safety checks) FGS memory refresh –Fixes SAA induced errors in FGS memory Safemode checks

Feb. 25, NSSC-I Hardware NSSC-I is the computer that is a major element of the SIC&DH (Science Instrument Command and Data Handling System) –SIC&DH has two redundant NSSC-Is, only one can be on at a time –SIC&DH has two redundant STINTs (interface units), paired with the NSSC-Is –Redundant unit has been off since launch –SIC&DH has 8 memory units, each with 8k 18 bit words Either NSSC-I can access full complement of memory SIC&DH hardware provides other standard services for SIs, under control of NSSC-I –Gathers science data from SIs and forwards on to spacecraft for recording or downlink –Gathers and formats engineering data from SIs and forwards on to NSSC-I and spacecraft –Provides command paths to SIs

Feb. 25,

Feb. 25, NSSC-I Flight Software Executive functions –Scheduling of activities 40 Hz basic interrupt cycle Table indicates functions to be executed in each 25 msec window, to spread CPU load –Engineering data collection and limit checks –Science data collection/output –Processes SI related stored commands –Miscellaneous special tasks Safing initiation PIT requests Re-use target offsets etc. Applications Processors –General facilities tuned to an SI –SI specific software

Feb. 25, Engineering data collection NSSC-I acts as single point contact for DF-224/SSM, collecting and forwarding engineering data for all SIs. –Small quantity of engineering data (RIU direct) bypasses NSSC-I –NSSC-I can provide an additional level of subcommutation to the data –Software variables can be collected as telemetry NSSC-I maintains a current value table in memory of all the SI engineering data. –This table is accessible to the SI specific application processors NSSC-I can maintain a table of up to 35 more parameters for each SI, which do not appear in the engineering telemetry –This table is also accessible to the SI specific applications processors –Used like the PITs, provides communication between SI computers and NSSC-I NSSC-I can maintain a table of up to 32 parameters per SI which are checked against allowable limits –This table is accessible to the SI specific applications processors –This table is typically used to provide SI health and safety checks, NSSC-I can respond to an out of limits by safing and/or error message

Feb. 25, Science Data Processing NSSC-I maintains the Standard Header Packet, and dumps it into the science stream on request –Uplinked programmatic information for data identification –Portions of each SIs Current Value Table –Copies of the most recent PIT tables –Unique data for each SI, provided by that SIs application processor NSSC-I can maintain the SI Unique Data Logs, and dumps them into the science stream on request –965 word log of data provided by an SI application processor –Now used only by FOC –Will not be used with future SIs (NICMOS UDL will be used for ASCS/NCS) NSSC-I can output science data processed by the NSSC-I –Used for GHRS target acquisitions –Not used for any current (or future) SIs

Feb. 25, NSSC-I stored command processing Absolute time processor –Command execution times have one second resolution –Implements basic SI timeline –By convention, does not execute any commands which reconfigure SI hardware –Can shut off entire processor, cannot shut off by SI –Currently mostly populated by data which gets forwarded to SI computers Relative time processor –Commands have delta time specifications, no absolute specifications –6 different processors can run at once, one for each SI and one for SIC&DH itself –Processors can be shut off individually (allows continuation of timeline with other SIs) –Common Pool Command sequences (RTCSs) are routinely loaded from the ground Some Common pool sequences are used for one-time execution (e.g. for a single exposure) Some Common pool sequences are permanently on-board –SI unique sequences are part of the code and not routinely changed Flight software can write SI-unique RTCSs which are then executed

Feb. 25,

Feb. 25, SI Application Processors FOC –Telemetry gathering –Health and Safety monitoring –Thermal control –Macro commands NICMOS –Communications with NICMOS CS (Control Section) via flags, etc. –Builds MACRO commands for CS Assembles and transmits data packet Sends activate command to CS –Health and Safety monitoring STIS (same as NICMOS) COSTAR –Health and Safety monitoring WFPC-II –Shutter control during long exposures –Health and Safety monitoring

Feb. 25, Safemode Protection Chain Computers pass “keep-alive” signals to one another –Roughly at once/second or faster rates –Value or flag which is different, at least on alternate cycles –Positive indication that the machine is still running Machine higher up the chain will force a safing of machine lower on the chain if keep-alives stop PSEA DF-224 NSSC-I WFPC-IINICMOSSTISFOC

Feb. 25, Communications System elements –TDRSS –High Gain Antennae –Low Gain Antennae –MA transponders –SSA transmitters Block diagram –Options –Redundancy

Feb. 25,

Feb. 25,

Feb. 25,

Feb. 25,

Feb. 25,

Feb. 25,

Feb. 25,