PCB Systems Division – Chelmsford, MA Introducing Constraint Manager for Allegro Designer & Allegro Performance Option Users PCB Systems Division – Chelmsford, MA

Availability Will be supplied post 14.2 first customer ship (FCS) Will NOT be part of PSD14.2 FCS disk set Will be made available through the ISR process ISR can be requested through Sourcelink or via http://software.cadence.com For a narrated movie of the tiered Constraint Manager Download the file “CM_DESIGNER14_2.avi” from Sourcelink

Preview your new Constraint Environment Managing Constraints in 13.6 Managing Constraints in 14.2 Constraint Manager User Interface Wiring Impedance Min/Max Propagation Delay Total Etch Length Relative Propagation Delay Electrical Constraint Sets Creating Buses

Introduction to Constraint Manager A spreadsheet based application to manage high speed electrical constraints across all the tools in the Cadence PCB Design Flow Powerful environment that lets you define, view and validate constraints in a highly productive manner Support of Min/Max Propagation Delay, Total Etch Length, Relative Propagation Delay, Impedance, Stub Lengths, Wiring schedules, Via Count, Parallelism, Exposed Length Hierarchical management of design objects Electrical Constraint Set or Net-Level based constraint management Easily create pin pairs from net level objects

Constraint Manager User Interface Object column ECSet reference Constraint values Worksheets In this example, the Routing workbook is opened to the Min/Max Propagation Delay worksheet. The Worksheet Selector also indicates which workbook and worksheets are open by coloring the gridded box next to each name. Each worksheet is a collection of columns some of which are based on the nature of the constraints the worksheet defines. These columns will be defined in the following slides.

Review of 13.6 Constraint Management Electrical Rule Set form Hierarchical Rules like Physical & Spacing Scheduling was driven by net level properties RATSNEST_SCHEDULE No list of pins Pin pair specific delays had to be placed on individual nets as net property overrides Forms interface for direct access to net level pin pair properties Applied to wide class of nets The Electrical Rule Set form was intended to be a hierarchical mechanism for setting Electrical constraints similar to the way Physical and Spacing constraints are handled. In other words, constraints are defined in sets and nets reference these sets. This works well for Physical and Spacing rules where a class of nets can reference the 5 mil rule set, for example. However, this form was too generic to effectively deal with electrical constraints and it was primarily used to turn on and off the various DRC modes and specific rules were set through Edit Properties. Electrical constraints may involve specific information about the target net and any type of pin pair specific rule is a good example. This form had no mechanisms for creating or logically applying such rules. User-defined scheduling was handled by commands (Net Schedule in Allegro, Pin Order in SQ) outside of this form. 13.6 CNS

Wiring Verify topology schedules Stub Length Via Count Exposed Length Parallelism

Impedance Target Impedance is compared against Actual Tolerance defined in percent or absolute value Margins identify the difference between actual and target.

Min/Max Propagation Delay Manage delay in terms of length, percent of manhattan length or time across pinpairs DRC responds to both unrouted and routed conditions Use to evaluate timing rules at the comp placement stage Selection of an object will highlight and zoom-center in Allegro

Total Etch Length Manage accumulated etch length across the entire net Accepts Min/Max conditions Fails represented in Red; Pass in Green Routed to Manhattan Ratio Listing Sorting capability for all columns.

Relative Propagation Delay Create matched groups between objects of different nets (scope=global) Use local option for relative delay within the same net Delta:Tolerance assigns a ‘target’ to object with longest manhattan length and can be reassigned if necessary Actual lengths reported

Electrical Constraint Sets (ECSETS) Vehicle for Hierarchical Constraint Management Collection of non-pin pair based constraints Apply at bus or net level

Buses Buses are groups of nets with common constraints Applying constraints at the highest level of hierarchy simplifies the process Buses can be expanded or collapsed Allegro provides a BUSRAT option in Setup > Drawing Options > Display