May 17, Design Option Trade-Offs w Transceiver Design - Dr. Zong Liang Wu, Philips

May 17, USB 2.0 Peripheral Design Options Zong Liang Wu Philips USB2.0 Transceiver and Device Architecture

May 17, Functional Building Blocks of a USB 2.0 Application System on a Chip of a USB 2.0 Function USB HS Analog Transceiver Application Specific Logic Micro-Processor HS PIE Parallel InterfaceEngine USB 1.1 SIE Serial Interface Engine USB backend ( endpoint configuration, system bus interface, DMA etc.) USB FS/LS Analog TransceiverTx:P-->S,BS,NRZI,SYNCgen.Rx:DLL,NRZI,BS, SYNC detect S-->P Clock circuitry, system logic D+D-

May 17, Q: How to Make Architectural Partitioning? w Purpose: Speed up the time to market for USB chips and USB application w This can be achieved by – Reusing existing cores / blocks (from 1.x) – Reducing risks due to functional errors (through FPGA-based prototyping) – Making reusable IP cores (for different application environments) w Background/reasons of Philips USB2.0 partitioning

May 17, HDLCodingHDLCoding Simulation FPGAReal-timeEmulation Tape-Out Main System Clock Must Allow HDL to Be Fpga-able (30mhz ?) Within an ApplicationEnvironment Normal Digital Block Design Flow Minimizing Risk Through FPGA Verification

May 17, USB2.0 Device Prototyping w Need a discrete 2.0 Transceiver w Map USB digital (& application specific) logic into an FPGA w Use a standard discrete micro-controller USB 2.0 (FS/HS)AnalogTransceiver+ Low-Level Digital Logic +Clocking USB 2.0 (FS/HS)AnalogTransceiver+ Low-Level Digital Logic +Clocking FPGA Application Specific LogicFPGA Logic HS PIE Parallel InterfaceE ngine USB 1.1 SIE Serial Interface Engine USB backend Standard Interface FPGA Discrete IC Micro- Processor Discrete IC Micro- Processor

May 17, USB2.0 Device: First Generation Product USB 2.0 (FS/HS)AnalogTransceiver+ Low-Level Digital Logic +Clocking USB 2.0 (FS/HS)AnalogTransceiver+ Low-Level Digital Logic +Clocking FPGA Application Specific LogicFPGA Logic HS PIE Parallel Interface Engine USB 1.1 SIE Serial Interface Engine USB backend Standard Interface Discrete IC Micro- Processor Discrete IC Micro- Processor USB ASIC Two/Three-Chip Solution: USB ASIC (+Micro-Processor) + Discrete 2.0 Transceiver

May 17, USB2.0 IP Cores w USB2.0 digital core – Generic interface on the backend side for wide application space w USB2.0 Transceiver core – Standard interface to the digital core (no change from prototyping to silicon integration) Generic Interface FPGA or Silicon Proven Standard Interface USB 2.0 (FS/HS)AnalogTransceiver+ Low-Level Digital Logic +Clocking USB 2.0 (FS/HS)AnalogTransceiver+ Low-Level Digital Logic +Clocking Application Specific Logic Logic HS PIE Parallel InterfaceE ngine USB 1.1 SIE Serial Interface Engine USB backend Silicon Proven Micro- Processor

May 17, Transceiver (IC/IP) Architectural Options w Clock-Switching: High speed clock for HS mode and scaled down clock for USB1.1 : – Scale clock to bits data-bus – Scale clock to bits data-bus – Scale clock to 3 4 bits data-bus w Over-Clocking: High speed clock for both HS and FS mode – --> Over-sampled parallel data bus for FS mode. (Intel’s USB2.0 Interface for IP) w Separate-Clocking: HS and FS use separate interfaces – No digital clocking in the Transceiver for FS mode – Single parallel data interface for HS only (+chirping) Fact: HS and FS Need Different Clock for Sampler, Data Recovery, Bit-stuffing, Data Coding in NRZI, etc.

May 17, Basic Considerations on Transceiver Architecture: Philips Perspective w Design reuse – Reuse knowledge and experiences of 1.1 Transceiver – Reuse 1.1 digital front-end (SIE) in a 2.0 device – Separate Full-Speed and High-Speed transceiver logic and interfaces w Enable easy reset, suspend, resume, transition between speed modes, and chirping w One basic Transceiver architecture for all (function, Host Controller & hub) w Making a discrete Transceiver IC to – Enable quick prototyping and testing/debugging of 2.0 devices and host controller – Enable two-chip solution products

May 17, OUT Token 6.5 bits for FS 192 bits for HS EOP SYNC ACK Basic Considerations on Transceiver Architecture: Philips perspective w Device Response Time Constraints – During a transaction, the device must respond within a time interval, otherwise the host will timeout – This time is from the end of the token’s EOP to the first synch bit of device’s response – This time is 6.5 bits for FS/LS device and – 192 HS bits for HS devices w The Transceiver should minimize the latency time (for both receive and transmit paths) for both FS and HS, in order to leave more time space for the digital core

May 17, HS PIE Parallel InterfaceE ngine HS PIE Parallel InterfaceE ngine 1.1 SIE Serial Interface Engine 1.1 SIE Serial Interface Engine Clock Circuitry + System Control Logic Clock Circuitry + System Control Logic FS Analog Drivers & Receivers FS HS HS HS Tx parallel->serial, BS, NRZI encoding HS Rx DLL, NRZI, BS, SYNC detection, serial-> parallel Legacy 1.1 interface D+D- Standard Interface for Function, Hub US Port and Host DS Port Transceiver Architecture 30MHz

May 17, Transceiver Architecture: Reset, Chirping, Suspend & Resume w Detection of bus reset, suspend condition: done in the digital core, with the RX_Inactive signaling from the HS Transceiver w When in suspend, all blocks are shut-off, only the single-ended receivers of the FS transceiver remain on, and the whole USB device termination is 1.1 w (Remote) Wakeup is done through FS transceiver w Chirping control logic can be done in either the Transceiver or the digital core (just at the interface level between the two cores)

May 17, Details About Philips Transceiver IC w Test samples available for key partners w Contact Marketing Manager W.L.Chui (see Marketing session) w Tel: