ECE 663 MOSFET I-Vs

Substrate Channel Drain Insulator Gate Operation of a transistor V SG > 0 n type operation Positive gate bias attracts electrons into channel Channel now becomes more conductive More electrons Source V SD V SG

Some important equations in the inversion regime (Depth direction) V T =  ms + 2  B +  ox W dm =  [2  S (2  B )/qN A ] Q inv = -C ox (V G - V T )  ox = Q s /C ox Q s = qN A W dm V T =  ms + 2  B +  [4  S  B qN A ]/C ox Substrate Channel Drain Insulator Gate Source x

ECE 663 MOSFET Geometry x y z L Z S D VGVG VDVD

ECE 663 How to include y-dependent potential without doing the whole problem over?

ECE 663 Assume potential V(y) varies slowly along channel, so the x-dependent and y-dependent electrostats are independent (GRADUAL CHANNEL APPROXIMATION) i.e., Ignore ∂ E x / ∂ y Potential is separable in x and y

ECE 663 How to include y-dependent potentials?  S = 2  B + V(y) V G =  S +  [2  S  S qN A ]/C ox Need V G – V(y) > V T to invert channel at y (V increases threshold) Since V(y) largest at drain end, that end reverts from inversion to depletion first (Pinch off)  SATURATION [V DSAT = V G – V T ]

j = qn inv v = (Q inv /t inv )v I = jA = jZt inv = ZQ inv v ECE 663 So current: Q inv = -C ox [V G – V T - V(y)] v = -  eff dV(y)/dy

ECE 663 So current: I =  eff ZC ox [V G – V T - V(y)]dV(y)/dy I =  eff ZC ox [(V G – V T )V D - V D 2 /2]/L Continuity implies ∫Idy = IL

ECE 663 But this current behaves like a parabola !! IDID VDVD I D sat V D sat I =  eff ZC ox [(V G – V T )V D - V D 2 /2]/L We have assumed inversion in our model (ie, always above pinch-off) So we just extend the maximum current into saturation… Easy to check that above current is maximum for V Dsat = V G - V T Substituting, I Dsat = (C ox  eff Z/2L)(V G -V T ) 2

What’s Pinch off? VGVG VGVG Now add in the drain voltage to drive a current. Initially you get an increasing current with increasing drain bias 0 VDVD VGVG VGVG When you reach V Dsat = V G – V T, inversion is disabled at the drain end (pinch-off), but the source end is still inverted The charges still flow, just that you can’t draw more current with higher drain bias, and the current saturates

Square law theory of MOSFETs I =  eff ZC ox [(V G – V T )V D - V D 2 /2]/L, V D < V G - V T I =  eff ZC ox (V G – V T ) 2 /2L, V D > V G - V T J = qnv n ~ C ox (V G – V T ) v ~  eff V D /L NEW

ECE 663 Ideal Characteristics of n-channel enhancement mode MOSFET

ECE 663 Drain current for REALLY small V D Linear operation Channel Conductance: Transconductance:

ECE 663 In Saturation Channel Conductance: Transconductance:

ECE 663 Equivalent Circuit – Low Frequency AC Gate looks like open circuit S-D output stage looks like current source with channel conductance

ECE 663 Input stage looks like capacitances gate-to-source(gate) and gate-to-drain(overlap) Output capacitances ignored -drain-to-source capacitance small Equivalent Circuit – Higher Frequency AC

ECE 663 Input circuit: Input capacitance is mainly gate capacitance Output circuit: Equivalent Circuit – Higher Frequency AC

ECE 663 Maximum Frequency (not in saturation) C i is capacitance per unit area and C gate is total capacitance of the gate F=f max when gain=1 (i out /i in =1)

ECE 663 Maximum Frequency (not in saturation) (Inverse transit time) NEW

ECE 663 Switching Speed, Power Dissipation t on = C ox ZLV D /I ON Trade-off: If C ox too small, C s and C d take over and you lose control of the channel potential (e.g. saturation) (DRAIN-INDUCED BARRIER LOWERING/DIBL) If C ox increases, you want to make sure you don’t control immobile charges (parasitics) which do not contribute to current.

ECE 663 Switching Speed, Power Dissipation P dyn = ½ C ox ZLV D 2 f P st = I off V D

ECE 663 CMOS NOT gate (inverter)

ECE 663 CMOS NOT gate (inverter) Positive gate turns nMOS on V in = 1V out = 0

ECE 663 CMOS NOT gate (inverter) Negative gate turns pMOS on V in = 0V out = 1

ECE 663 So what? If we can create a NOT gate we can create other gates (e.g. NAND, EXOR)

ECE 663 So what? Ring Oscillator

ECE 663 So what? More importantly, since one is open and one is shut at steady state, no current except during turn-on/turn-off  Low power dissipation

ECE 663 Getting the inverter output Gain ON OFF

ECE 663 What’s the gain here?

ECE 663 Signal Restoration

ECE 663 BJT vs MOSFET RTL logic vs CMOS logic DC Input impedance of MOSFET (at gate end) is infinite Thus, current output can drive many inputs  FANOUT CMOS static dissipation is low!! ~ I OFF V DD Normally BJTs have higher transconductance/current (faster!) I C = (qn i 2 D n /W B N D )exp(qV BE /kT) I D =  C ox W(V G -V T ) 2 /L g m =  I C /  V BE = I C /(kT/q) g m =  I D /  V G = I D /[(V G -V T )/2] Today’s MOSFET I D >> I C due to near ballistic operation NEW

ECE 663 What if it isn’t ideal? If work function differences and oxide charges are present, threshold voltage is shifted just like for MOS capacitor: If the substrate is biased wrt the Source (V BS ) the threshold voltage is also shifted

ECE 663 Threshold Voltage Control Substrate Bias:

ECE 663 Threshold Voltage Control-substrate bias

ECE 663 It also affects the I-V VGVG The threshold voltage is increased due to the depletion region that grows at the drain end because the inversion layer shrinks there and can’t screen it any more. (W d > W dm ) Q inv = -C ox [V G -V T (y)], I = -  eff ZQ inv dV(y)/dy V T (y) =  + √2  s qN A  / C ox   = 2  B + V(y)

ECE 663 It also affects the I-V IL = ∫  eff ZC ox [V G – (2  B +V) - √2  s qN A (2  B +V)/C ox ]dV I = (Z  eff C ox /L)[(V G –2  B )V D –V D 2 /2 -2√2  s qN A {(2  B +V D ) 3/2 -( 2  B ) 3/2 }/3 C ox ]

ECE 663 We can approximately include this… Include an additional charge term from the depletion layer capacitance controlling V(y) Q = -C ox [V G -V T ]+(C ox + C d )V(y) where C d =  s /W dm Q = -C ox [V G –V T - MV(y)], M = 1 + C d /C ox I D = (Z  eff C ox /L)[(V G -V T - MV D /2)V D ]

ECE 663 Comparison between different models Square Law Theory Body Coefficient Bulk Charge Theory Still not good below threshold or above saturation

ECE 663 Mobility Drain current model assumed constant mobility in channel Mobility of channel less than bulk – surface scattering Mobility depends on gate voltage – carriers in inversion channel are attracted to gate – increased surface scattering – reduced mobility

ECE 663 Mobility dependence on gate voltage

ECE 663 Sub-Threshold Behavior For gate voltage less than the threshold – weak inversion Diffusion is dominant current mechanism (not drift)

ECE 663 Sub-threshold We can approximate  s with V G -V T below threshold since all voltage drops across depletion region Sub-threshold current is exponential function of applied gate voltage Sub-threshold current gets larger for smaller gates (L)

ECE 663 Subthreshold Characteristic Subthreshold Swing

Tunneling transistor –Band filter like operation J Appenzeller et al, PRL ‘04 Ghosh, Rakshit, Datta (Nanoletters, 2004) (S conf ) min =2.3(k B T/e).(et ox /m) Hodgkin and Huxley, J. Physiol. 116, 449 (1952a) Subthreshold slope = (60/Z) mV/decade Much of new research depends on reducing S !

Increase ‘q’ by collective motion (e.g. relay) Ghosh, Rakshit, Datta, NL ‘03 Effectively reduce N through interactions Salahuddin, Datta Negative capacitance Salahuddin, Datta Non-thermionic switching (T-independent) Appenzeller et al, PRL Nonequilibrium switching Li, Ghosh, Stan Impact Ionization Plummer

ECE 663 More complete model – sub-threshold to saturation Must include diffusion and drift currents Still use gradual channel approximation Yields sub-threshold and saturation behavior for long channel MOSFETS Exact Charge Model – numerical integration

ECE 663 Exact Charge Model (Pao-Sah) – Long Channel MOSFET

ECE 663