Layout of the Power Distribution on Support Tube for Phase I Lutz Feld, Waclaw Karpinski, Katja Klein, Jan Sammet, Michael Wlochal

Pixel Phase-I Powering System 2Waclaw KarpinskiGrindelwald

Support Tube 3 two half shells of each side of the pixel detector 8 slots/half shell equipped with power distribution and readout and control electronics up to 26 DCDC converters per slot located in segment A CO 2 cooling pipes pass through slots and are used to cool DCDC converters and optohybrids the middle slot is equipped with BPIX cooling pipes and auxiliary power cables 26 DC-DC Converters 14 x POH DOHs+TPLLs+Delays25 Connector Boards Pixel modul cables Adapter Boards CCUM Waclaw KarpinskiGrindelwald

Power distribution in a slot 4 Segment A Segment B Segment C Segment B Bus Board with DCDC Converters Connector Board L4 Extensions Boards Connector Board L3 Connector Board L1&L2 Module Cables Multiservice Cables “Bus-Board” equipped with up to 26 DCDC-converters in segment A segment B equipped with 2 x Extension Boards segment C equipped with 2 x „adapter boards“, 3 x „connector boards“ copper cladded aluminium wires Ø 360 µm across segment D Long distance of 2.2m from flange to detector modules Waclaw KarpinskiGrindelwald

5 Converter Bus Board layer 1 layer 4 layer 2 layer 3 slow control connector (DF20F-30DP-1H) digital converter analogue converter served by cable 1 served by cable 2 cable 2 cable 1 Bus Board distributes power and controls to DCDC converters transmits bias voltages converters organized in 13 pairs (analog and digital) two MSC power the DCDC converters of one slot 60 Rigid part of the cable Waclaw KarpinskiGrindelwald

6 Converter Bus Board power dissipation ~ 35W per slot anodized aluminium cooling bridges screwed around CO2 cooling pipes used to cool the converters the cooling bridges are electrically insulated from the converters 8-layer PCB Cu thickness: 70 µm per layer size: 488mm x 40mm x 1.6mm Waclaw KarpinskiGrindelwald

Tests of the Bus-Board Prototype 7 a prototype board for 16-facette version under test, using dummy loads  Temperature checked with infrared camera, looks ok  Voltage drops across board agree reasonably well with calculations Waclaw KarpinskiGrindelwald

Accelerated aging studies 8 Cycles with bus board and converter dummies under nominal load 4 cycles per day, -10°C to +40°C (coolant temperature) Test duration: 30 days Waclaw KarpinskiGrindelwald

Accelerated aging studies 9  Voltage drop on bus board is as expected  No change in quality of connections after 120 thermal cycles within 30 days Waclaw KarpinskiGrindelwald

Segment B 10 Extension Board L1&L2 753mm x 40mm x 05mm Crossover A-B Crossover B-C Extension boards are flexible two-metal-layer kapton pcbs Contain in total 26 power rails+2 Power_Return_Rails+15 HV lines+ 4HV_GND lines Cu thickness = 100 µm Isolation made by two layers of Vacrel-Soldermask Waclaw KarpinskiGrindelwald Extension Board L3&L mm x 40mm x 0.5mm

Supply Currents and Voltages at the ROCs 11 Expected max. Digital Supply Current [A] Expected max. Analog Supply Current Expected Analog Supply Voltage [V] Expected Digital Supply Voltage [V] Calculations made for converter input voltage =10V, analogue c. output =2.5V, digital c. output = 3.0V, efficiency = 80%, Luminosity = 2x Waclaw KarpinskiGrindelwald absolute minimum voltage margin ~160 mV for digital supply and ~ 300 mV for analog supply

Calculated max. Voltage Drop on Power Lines 12 Digital Lines Analog Lines [V] Waclaw KarpinskiGrindelwald

Control of DCDC Converters 13 each converter has one power good output and one enable input control will be made via the parallel IOs of CCU converters will be controlled by pairs: an analogue and a digital converter feeding power to the same pixel modules one CCU controls 13 converter pairs and 2x mDOH + 2xTPLL + 2 x Delay25 ASICs located in one slot the control-ring will be a flexible kapton pcb equipped with 2 x DOHs, 9 x CCUs and 9 x LVDSMUX 13 location of the CCU-rings in a slot 46 mm Waclaw KarpinskiGrindelwald

Grounding 14 The dcdc conveters of one slot are powered from one PS A4603 One A4603 houses two ”Power Supply Units” PSU0 and PSU1, delivering two HV channels with common floating return and two LV channels (analog and digital supply ) also with common floating return each The LV-returns of the two PSU are short circuited on the Bus Board →There is only one LV-Return in a slot One floating auxiliary power channel powers the control components corresponding to one slot The control ring is powered by one floating power channel the electronics installed in a slot should be grounded at one point the grounding points of all slots should be interconnected the grounds of both half shells should be interconnected Waclaw KarpinskiGrindelwald

Grounding schema 15 Vdrop 60mV 90mV 60mV100mV Common Ground should be located as close as possible to the detector the voltage difference between CCU_GND and Converter_GND should be <0.2V → two options: Common Ground at the transition between segments B and C or alternatively at the transition between segments A and B The pixels modules must be isolated from the support structure Waclaw KarpinskiGrindelwald 46A

HV - Isolation 16 all HV lines (15) are arranged in 4 groups : L1 & L2 (1000V) and L3 &L4 (600V) the isolation distance between groups = 0.5 mm in min. safe up to 600V according to IPC 2221 the clearance between HV-lines in a group = 0.25 mm safe up to 500V according to IPC 2221 clearance between the connectors HV-Pins = 0.63mm → safe up to 150V according to IPC Waclaw KarpinskiGrindelwald

HV-Isolation V 0.5mm 1.0mm 1.0mm 1.8mm 1000V 1.5mm 2.2mm 2.2mm 3.0mm Inner layer surface of pcb under a solder mask components leads coated components leads uncoated IPC 2221 defined clearances : Need to define HV-insulation rules with reduced clearances which will still guarantee safe functionality of pixel electronics On Pixel-HDI the clearances amount to 0.6mm in air and 0.37 mm under the solder mask. In the cable connector in PP1/PP0 the clearance amounts to 1.76mm Waclaw KarpinskiGrindelwald

Proposal with improved HV - insulation 18 Additional flexible board containing all HV Lines and HV - Returns Connector Board Layer 1 & 2 Connector Board Layer 3 Connector Board Layer 4 Size: ~1330mm x 35mm x 0.3 mm New HV-Board Bus-Board Waclaw KarpinskiGrindelwald

integration of power system on support tube is in progress prototype of Bus-Board has been build and tested  measured voltage drops across board agree reasonably well with calculations  accelerated aging study show no changes in quality of connections after 120 thermal cycles within 30 days calculated voltage drops on power rails can be tolerated –expected safety margin ~160 mV for digital and 300 mV for analog supply at the ROCs New design with improved HV – Isolation performance is proposed There is a need to define HV-isolation rules with reduced clearances which will guarantee safe operation of the electronics in Pixel-Detector environment Summary Waclaw KarpinskiGrindelwald19

20 Buck-Up Slides Waclaw KarpinskiGrindelwald

21 DCDC-Converter (present version) PCB: 2 copper layers a 35µm 0.3mm thick Large ground area on backside for cooling Toroidal Inductor: L = 450nH R DC = 40m  Shield/heat sink copper-plated plastic cap soldered to pcb AC_PIX_V8 A 2.8cm x 1.6cm; ~ 2.0g Pi-filters at in- and output ASIC : AMIS4 by CERN I out < 3A V in < 10V V out configurable; (here: 2.4V & 3.0V) f s configurable, e.g. 1.5MHz Waclaw KarpinskiGrindelwald

AMIS4 ASIC 22 Features: Bandgap and 4 linear regulators integrated Dead time handling with adaptive logic Triplication and logic against SEU Improved power transistor design wrt TID Over-current protection Over-temperature protection Input under-voltage protection State machine for soft start-up procedure, handling of protection Power Good output Enable input Waclaw KarpinskiGrindelwald

HV Lines 23Waclaw KarpinskiGrindelwald

24 Power distribution crossover B-C Print A (Layer 1 & 2) Print B (Layer 3) Print C (Layer 4) Power Bus Layer 1 & 2 Power Bus Layer 3 & 4 mDOH & PLL & Delay25 Waclaw KarpinskiGrindelwald

25 Calculated Voltage Drop on Power Lines for Layer 1 & 4 Calculations are made for converter input voltage =10V, analogue c. output =2.5V, digital c. output = 3.0V, efficiency = 80% at the ROC input nominal analogue voltage = 1.6V and nominal digital voltage = 2.2V Luminosity = 2 x Pos.ConverterNet Name Converter Output Current Voltage Drop Sector A 8 Layers (70 µm Cu ) Voltage Drop Sector B 2 Layers (100 µm Cu ) Voltage Drop Sector C 4 Layers (35 µm Cu ) Voltage Drop Sector D AL-Draht Ø 350 µm Voltage Drop Total in Sectors A-D Voltage at the ROC [A][V] 0L1C1D0D0C L1C1D1D1C L1C1D2D2C L4C1D3D3C L4C1D4D4C L4C1D5D5C L4C1D6D6C L1C1A0A0C L1C1A1A1C L1C1A2A2C L4C1A3A3C L4C1A4A4C L4C1A5A5C L4C1A6A6C Waclaw KarpinskiGrindelwald

26 Calculated Voltage Drop on Power Lines for Layer 2 & 3 Calculations are made for converter input voltage =10V, analogue c. output =2.5V, digital c. output = 3.0V, efficiency = 80% at the ROC input nominal analogue voltage = 1.6V and nominal digital voltage = 2.2V Luminosity = 2 x Pos.ConverterNet Name Converter Output Current Voltage Drop Sector A 8 Layers (70 µm Cu ) Voltage Drop Sector B 2 Layers (100 µm Cu ) Voltage Drop Sector C 4 Layers (35 µm Cu ) Voltage Drop Sector D AL-Draht Ø 350 µm Voltage Drop Total in Sectors A-D Voltage at the ROC [A][V] 7L2C2D7D1C L2C2D8D2C L2C2D9D3C L3C2D10D4C L3C2D11D5C L3C2D12D6C L2C2A7A1C L2C2A8A2C L2C2A9A3C L3C2A10A4C L3C2A11A5C L3C2A12A6C Waclaw KarpinskiGrindelwald

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