Microcomputer & Interfacing Lecture 2 8086 Microprocessor BY: Tsegamlak Terefe

Pin outs & Signal Description Interfacing Objective Pin outs & Signal Description Interfacing BY: Tsegamlak Terefe

Pin outs & Signal Description 8086 is a 40 pin DIP packaged microprocessor which can operate in two modes known to be maximum & minimum modes of operation. Max Mode: in this mode the 8086 processor is accompanied by another co-processor. Min Mode: in this mode the 8086 processor will be a stand alone microprocessor. Three clock mode of operation with 33% duty cycle. 5MHz,8MHz,10MHz Note: since the processor have two modes of operation the pins are categorized in to three generalizations. pins/ signals that are for minimum mode. Pins/signals that are for maximum mode. Pins/signals that are for both maximum and minimum mode. We will start the pin/signal description which are common for both maximum and minimum mode. One thing to note here is that in max mode some important signal pins are replaced in order to compensate for this an additional bus controller is needed in max mode. BY: Tsegamlak Terefe

Pin outs & Signal Description Requires +5V power supply. Pin as an input Pin as an output For more than 10 outputs per pin buffering is required. BY: Tsegamlak Terefe

Pin outs & Signal Description BY: Tsegamlak Terefe

Pin outs & Signal Description common to Max and Min The address/data Bus AD0-AD15 : This are time multiplexed address/data bus. Address will be available on T1 while data will be available from T2-T4 . This lines will become tri stated if the bus is needed for DMA/ hold is acknowledged. Address/ Status lines A16-A19/S3-S6 : Time multiplexed status and address bus. On T1 an address is available on A 16-A19 while status is available on the rest of the bus cycles. BY: Tsegamlak Terefe

Pin outs & Signal Description common to Max and Min S6 is always 0, S5 shows Interrupt(IF),S3 & S4 show which segment is being accessed. /RD: when this signal is 0 the data bus is receptive to data from I/0 or Memory. BY: Tsegamlak Terefe

Pin outs & Signal Description common to Max and Min Ready: This pin used to insert a wait cycle in to the timing of the processor. Putting this pin at 0 level will insert wait cycles. INTR: Setting this pin to high will cause a hardware interrupt if and only if IF (S5)Is high. Interrupts will be allowed after the instruction at hand completes execution. /Test: This is a pin associated with a wait instruction. If pin is set to low wait is executed as NOP else the processor waits until pin becomes low. NMI: This pin is similar to INTER except that IF is not checked if pin is set to high. BY: Tsegamlak Terefe

Pin outs & Signal Description common to Max and Min RESET: If this pin is set to high will cause the processor to reset. It will require 4 clock periods for the processor to rest. After reset the processor start executing instructions at FFFF0H. CLK: This pin is used as a clocking pin for the processor. VCC: This pin is used to power up the processor. GND: Is used as a return path for the power supply of the processor. MN/(/MX): This pin used to select minimum /maximum mode. If set to high processor is at minimum mode of operation. /BHE/S7: This pin used as a bus high enable which will make the most significant data bits (D7-D15) available if set to low. S7 is always high. BY: Tsegamlak Terefe

Pin outs & Signal Description Minimum mode M/(/IO): This pin will indicate if the processor address bus contain a memory of an I/O address . /WR : This will indicate if the processor is outputting data to a memory of I/O device. /INTR: This pin acknowledges to an interrupt request at the INTR pin. This pin is also used to output the interrupt vector number on the data bus. ALE: This pin will indicate that the bus holds an address . The pin will not float to a hold acknowledgment. BY: Tsegamlak Terefe

Pin outs & Signal Description Minimum mode DT/(/R): This pin is used to indicate if the data bus is transmitting or receiving. This pin is used to enable external buffers. DEN: activates external data bus buffer. HOLD: is used to request for DMA. HOLDA: is used to acknowledge a hold request. /SS0: Is used to indicate the function of current bus cycle with the combination of DT/(/R) and M/(/IO). BY: Tsegamlak Terefe

Pin outs & Signal Description Minimum mode BY: Tsegamlak Terefe

Pin outs & Signal Description Maximum mode /S0,/S1,/S2 : shows the function of the current bus cycle. /R0,/GT0,/R1,/GT1 : This pin will function as a Bi-direction access request and grant for DMA. /LOCK: This pin is used to lock peripherals off the system. QS1, QS0 : This bits will indicate the status of the internal queue. BY: Tsegamlak Terefe

Pin outs & Signal Description Maximum mode BY: Tsegamlak Terefe

Interfacing Memory BY: Tsegamlak Terefe

Interfacing [Memory] 8086 Have Bus cycles which is a mechanism used to multiplex address and data busses. The bus cycle is made of four µP clock cycles at minimum. For Example if the processor is running at 5MHz one bus cycle will become 800ns making it able to do 1.25M instruction per second. Note1: A bus cycle by definition is four processor clock cycle. But, in times of read and write operations external devices might require additional time to perform effectively. Hence, additional clocks Known as Wait(Tw) are inserted between T2 and T3 which will decrease 1.25M instructions per second performance. Note2: One simple fact is that Bus is needed when there is a data movement or an instruction fetching is required. Hence, whenever this happens the first bus cycle is allocated for broadcasting the required address to memory which is followed by status information and the appropriate signal to read and write to a memory. One question that should be raised in your mind by now should be how will the memory know the address if we remove the address from the line while the read and write signals are active. Well here is where your Digital Logic course comes to the rescue I hope you already have heard the word Latch. BY: Tsegamlak Terefe

Interfacing [Memory] A read and Write operations will follow the following timing diagram . Write timing diagram Note: You could simply observe that address is available to memory through out the bus cycle since address is latched on T1. in addition to this data is written to the memory at the end of T3 when the /WR strobe changes from zero to one. For instance for a clock of 5MHz this critical time will be 88ns hence a memory device you are going to interface to 8086 at most should have 88ns write time. Diagrams of this kind will tell you what kind of memory you can interface with a given processer for a normal operation. You should refer the detailed timing diagram on the data sheet for further information. BY: Tsegamlak Terefe

Interfacing [Memory] A read and Write operations will follow the following timing diagram . Read timing diagram Note: A read operation is similar to a write operation the only difference Is that data bus is sampled at the end of T3. In addition to this a detailed read timing diagram on the data sheet will tell you the memory access time i.e. the time from T1-T3. This detailed timing diagram will help you to identify what kind of memory products you can interface with 8086 since the memory access time is a thing to get your mind on while interfacing. BY: Tsegamlak Terefe

Interfacing [Memory] BY: Tsegamlak Terefe

Interfacing [Memory] A simple typical memory device will have Address input pins Data Input/output pins Control signals for read, write, select Mostly Memory is defined as XKB x no of data bit per row Eg. 64KBx8 Note: It should not be taken all memory devices will have only this pins. BY: Tsegamlak Terefe

Interfacing [Memory] 2KX8 SRAM 2KX8 ROM BY: Tsegamlak Terefe Note: as you can observe from this simple examples there is a difference in address pins between the memory and the 8086 hence you need decoding of addresses to account for this mismatch. In addition to this there is also a mismatch between the data lines of memory and 8086 hence you need to organize some kind of memory data line mapping mechanism (banking). BY: Tsegamlak Terefe

Interfacing [Memory] BY: Tsegamlak Terefe Note: It should not be taken all memory devices will have only this pins. BY: Tsegamlak Terefe

Interfacing [Memory] LATCH (8282) 8086 Memory (up to 1MB) TRANSCEIVER AD15-AD0 8086 Memory (up to 1MB) A19-A16 LATCH (8282) TRANSCEIVER (8286) Address Data BY: Tsegamlak Terefe

Interfacing [Memory] During T1 the address latch is enabled using the signal ALE (ALE = 1) After T1 the data transceiver is enabled using the signal DEN ( DEN = 0) Since the data line is bidirectional, the signal named DT/ R is used to select direction of data 𝐷𝑇/ 𝑅 = 0 From memory to 8086 𝐷𝑇/ 𝑅 = 1 From 8086 to memory BY: Tsegamlak Terefe

Interfacing [Memory] LATCH (8282) 8086 Memory (up to 1MB) TRANSCEIVER AD15-AD0 8086 Memory (up to 1MB) A19-A16 LATCH (8282) TRANSCEIVER (8286) Address Data 𝐷𝐼𝑅   BY: Tsegamlak Terefe

Interfacing [Memory] Due to the fact that 8086 processor involves a byte access instructions the 8086 memory is organized as an odd(D15-D8) and even(D7-D0) bank memory locations. Note: in addition to this fact memory devices at that time have an 8 bit pin data bus hence banking memory into even and odd seems a legitimate option to take in decoding which also made it possible to be backward compatible with predecessors(8085 & 8080) which have 8 data pins. BY: Tsegamlak Terefe

Interfacing [Memory] A memory bank to be accessed is selected using the signals A0(AD0) and 𝐵𝐻𝐸 𝐁𝐇𝐄 A0 Access Indications Whole word (16-bits) 1 Upper byte from odd address Lower byte from even address None BY: Tsegamlak Terefe

Interfacing [Memory] 8086 Lower Bank LATCH (8282) TRANSCEIVER (8286) AD15-AD0 8086 Lower Bank A19-A16 LATCH (8282) TRANSCEIVER (8286) Upper Bank A19-A1 D15-D8 D15-D0   ALE     D7-D0     BY: Tsegamlak Terefe

Interfacing [Memory] BY: Tsegamlak Terefe Note: an example memory address decoding. BY: Tsegamlak Terefe

Interfacing [Memory] BY: Tsegamlak Terefe

I/O Two ways to interface input out devices are available for the processor Memory Mapped I/o Isolated I/o Memory Mapped I/O : The I/O devices use some portion of the available 1MB memory range. In this mode there are no special instructions to transfer data between the processor and the I/O devices. Note: The 8086 can also operate as 8bit I/0 address. If the processor is operating in this mode care should be taken so that data is saved at the low memory bank. BY: Tsegamlak Terefe

I/O Isolated I/O: In this mode of interfacing I/O devices will have separate memory available for them. For the 8086 I/O is addressed either in 8 bit (Fixed I/O) or 16 bit (Variable I/O). Hence, 64KB of memory is needed for interfacing I/O devices. DX is used to hold 16 bit port address for I/O. Note: since you have been shown how to interface memory the I/0 operation will be some how similar but the M/IO pin will be used to separate if an IO or memory operation is taking place. BY: Tsegamlak Terefe

Next Next Class 8086 instruction Sets Further reading 1. Dr. Manoj’s handout (chapter 1) 2.[Barry_B._Brey]_The_Intel_Microprocessors_8086 (practical examples on decoding and interfacing of memory (chapter 8, 9)) BY: Tsegamlak Terefe