Chemical Vapor Deposition This presentation is partially animated. Only use the control panel at the bottom of screen to review what you have seen. When.

Slides:



Advertisements
Similar presentations
MICROELECTROMECHANICAL SYSTEMS ( MEMS )
Advertisements

FABRICATION PROCESSES
CHAPTER 8: THERMAL PROCESS (continued). Diffusion Process The process of materials move from high concentration regions to low concentration regions,
Chapter 2 Modern CMOS technology
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Oxidation.
OXIDATION- Overview  Process Types  Details of Thermal Oxidation  Models  Relevant Issues.
Ksjp, 7/01 MEMS Design & Fab IC/MEMS Fabrication - Outline Fabrication overview Materials Wafer fabrication The Cycle: Deposition Lithography Etching.
1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Chemical Vapor Deposition.
The Deposition Process

ECE/ChE 4752: Microelectronics Processing Laboratory
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #5.
Thin Film Deposition Prof. Dr. Ir. Djoko Hartanto MSc
A. Transport of Reactions to Wafer Surface in APCVD
Surface micromachining
Film Deposition in IC Fabrication
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.
McGill Nanotools Microfabrication Processes
Lecture 12.0 Deposition. Materials Deposited Dielectrics –SiO2, BSG Metals –W, Cu, Al Semiconductors –Poly silicon (doped) Barrier Layers –Nitrides (TaN,
Fabrication of Active Matrix (STEM) Detectors
반도체 제작 공정 재료공정실험실 동아대학교 신소재공학과 손 광 석 隨處作主立處開眞
Plasma-Enhanced Chemical Vapor Deposition (PECVD)
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 
Lecture 2.0 Thermodynamics in Chip Processing Terry Ring.
Carrier Mobility and Velocity
PVD AND CVD PROCESS Muhammed Labeeb.
Gas-to Solid Processing surface Heat Treating Carburizing is a surface heat treating process in which the carbon content of the surface of.
Chapter 9 Thin Film Deposition
SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.
Thermodynamics in Chip Processing II Terry A. Ring.
Semiconductor Manufacturing Technology Michael Quirk & Julian Serda © October 2001 by Prentice Hall Chapter 9 IC Fabrication Process Overview.
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Reminders Quiz#2 and meet Alissa and Mine on Wednesday –Quiz covers Bonding, 0-D, 1-D, 2-D, Lab #2 –Multiple choice, short answer, long answer (graphical.
Dry Etching + Additive Techniques
Top Down Manufacturing
Thermal doping review example This presentation is partially animated. Only use the control panel at the bottom of screen to review what you have seen.
Top Down Method Etch Processes
Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.
EMT362: Microelectronic Fabrication Interlevel Dielectric Technology
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
BY KRISHNAN.P Chemical Vapour Deposition (CVD) is a chemical process used to produce high purity, high performance solid materials. In a typical.
Midterm Exam Question (Thermal doping review) This presentation is partially animated. Only use the control panel at the bottom of screen to review what.
Thin Film Deposition. Types of Thin Films Used in Semiconductor Processing Thermal Oxides Dielectric Layers Epitaxial Layers Polycrystalline Silicon Metal.
Mar 24 th, 2016 Inorganic Material Chemistry. Gas phase physical deposition 1.Sputtering deposition 2.Evaporation 3.Plasma deposition.
Top Down Method The Deposition Process Author’s Note: Significant portions of this work have been reproduced and/or adapted with permission from material.
ALD coating of porous materials and powders
KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering Lecture V Thermal Processes.
Deposition Techniques
Mass Transfer transport of one constituent from a region of higher concentration to that of a lower concentration.
CVD & ALD
Lecture 3: Semiconductor Epitaxy Technologies (II) and
서강대학교 기계공학과 최범규(Choi, Bumkyoo)
Fabrication Process terms
Microelectronic Fabrication
III. Thin film deposition
Lecture 4 Fundamentals of Multiscale Fabrication
Modern Semiconductor Devices for Integrated Circuits (C. Hu) Slide 3-1 Chapter 3 Device Fabrication Technology About transistors (or 10 billion for.
PVD & CVD Process Mr. Sonaji V. Gayakwad Asst. professor
Silicon Wafer cm (5’’- 8’’) mm
Deposition 27 and 29 March 2017 Evaporation Chemical Vapor Deposition (CVD) Plasma-Enhanced Chemical Vapor Deposition (PECVD) Metal Organometallic CVD.
Thermal oxidation Growth Rate
Lecture 3: Semiconductor Epitaxy Technologies (II) and
Metal Organic Chemical Vapour Deposition
Deposition Techniques 5 and 8 April 2019
Deposition 30 March And 1 April 2016
Basic Planar Process 1. Silicon wafer (substrate) preparation
Presentation transcript:

Chemical Vapor Deposition This presentation is partially animated. Only use the control panel at the bottom of screen to review what you have seen. When using your mouse, make sure you click only when it is within the light blue frame that surrounds each slide.

Introduction to Chemical Vapor Deposition A) Chemical Vapor Deposition CVD Types CVD Uses CVD Process General CVD Reactor Concept General CVD Process Advantages General CVD Process Applications B) Dealing with Engineering Science of CVD Reactions Transport Processes Laminar Flow Boundary Layer Concept Other Susceptor to Flow Axis Options Thermodynamics Reaction Kinetics C) Operational Overview Polycrystaline Silicon Silicon Dioxide Nitride Films

LPCVD APCVD PECVD Chemical Vapor Deposition Current Options Atmospheric Pressure CVD Plasma Enhanced CVD Low Pressure CVD

CVD Silicon Nitride Silicon dioxidePolycrystalline Silicon Epitaxial Layers Customized Surfaces InsulatorConductors Barriers Chemical Vapor Deposition CVD Applications

Arrival Flow Rate Substrate Input Flow Rate r = Growth Rate of Film g r g Surface Reaction Rate Growth Rate Film Chemical Vapor Deposition CVD Process Surface Reaction

CVD Reactor Concept Reaction Chamber Susceptor Controlled Thermal Environment Controlled Pressure Environment

General CVD Process Advantages Excellent Step Coverage Large Throughput (100 A/min film growth) Low Temperature Processing (450 to 1000 C) Applicable to any Vaporization Source Technology (Laser CVD for direct Writing) General CVD Process Applications Epitaxial Films Enhance performance of Discreet and Integrated Bipolar Devices Allow Fabrication of RAM’s and CMOS in Bulk Substrate Dielectrics Insulation between Conducting Layers Diffusion and Ion Implant Masks Capping Dopant Films Extracting Impurities Passivation to Protect Structures from Impurities Moisture Scratches Polysilicon Conductors Gate Electrodes Conductors for Multilevel Metalizations Contacts for Shallow Junction Devices

B) Dealing with Engineering Science of CVD Reactions Transport Processes Thermodynamics Reaction Kinetics Transport Processes Turbulent FlowNo, to Many Particles. Molecular FlowNo, to Low a Throughput Laminar Flow ( Only One Left, Make Do) Set Conditions For Laminar Flow ( Low Reynolds Number Value)

R = D V ( ) Reynolds Number Linear Velocity Tube Diameter # D µ Gas Density Gas Viscosity

Laminar Flow Conditions Diameter and velocity in tens of cm and cm/s will give Reynolds numbers in laminar flow regime R = 1.76 x 10 5 Growth ( D /R) (1/ T ) 1.67 ( T/ y ) (Z) P) Boundary Layer Thickness Reagent Partial Pressure $ Reagent’s Gas Phase Coefficient of Thermal Diffusion $ ' " % 0.33

Susceptor Input Reactant Gas Flow Boundary layer develops along susceptor flow axis X 1 X 2 X 3 X 4 Graphic Exaggerated for Visual Effect Distance Above Susceptor

Trends in Gradients Velocity Values Increase Along Susceptor Increase Above Susceptor Temperature Values Increase Along Susceptor Decrease Above Susceptor Reactant Concentration Value Decrease Along Susceptor Increase Above Susceptor

Other Susceptor to Flow Axis Options Design Factors Include Flow Direction and Wafer Angle A) Input gas flow B) Input gas flow C) Input gas flow D) Input gas flow E) Input gas flow

Thermodynamics CVD Phase Diagram Give range of input conditions for CVD that could produce specific condensed phases. Presented as Function of Temperature or Pressure vs Mole Fraction. Boron codeposit only in High Boron Mole Fractions in input stream Boron codeposition favored at higher pressures o C 1000 o C 1400 o C Reactant Gas Mole Fraction B/(Ti + B) 0.01 Atm 1.0 Atm 0.6 TiB 2 Phase H/HCl = 0.95 Use Graphic for Educational Value Only 7 th Conference on CVD 1979 K.E. Spear Electrochemical Society Vol 79 TiB 2 & B Phase

BCl 3 /CH 4 = 4 Use Graphic for Educational Value Only J. Electrochem. Soc.123,136, 1976 Bernard Ducarroir Partial Pressure for Methane B 4 C + C B 4 C B 4 C + B B Carbon Vapor C 1.0 Atm Boron-Carbon CVD Phase Diagrams

Vanadium-Silicon-Hydrogen-Chloride CVD Phase Diagrams

Reaction Kinetics Use Graphic for Educational Value Only 124, 790 (1979) Besmann,J. Electrochem. Soc. 1/T (x 10 / K) Titanium Diboron Deposition Arrhenius Plot P = Atm. Input flow Rate = 462 cc /min B/(B + Ti) = 0.66 Cl/(Cl + H) = 0.33 Input Gases TiCl 4 BCl 3 H 2 Reaction Temperatures (2000K to 1000K)

Use Graphic for Educational Value Only Arrhenius Rate Profiles

Use Graphic for Educational Value Only Partial Pressure Reactant Gas Arrhenius Isotherms (a) (f) Surface Reaction Limiting Growth Rate

ln(r g2 /r g1 ) ' (q + act /k)(T 2 & T 1 /T 2 T 1 )

C) OperationalOverviews Polycrystalline Silicon (Polysilicon) Four popular ways to alter pressure. Change gas flow rate but keep pumping speed constant. Change pumping speed with constant flow rate Change reacting gas or carrier gas with other held constant Change both gases but keep there ratio constant. Considerations Temperature Pressure (LPCVD) Si H HH H 25 PA to 130 PA 100% Silane 25 PA to 130 PA 20% to 30% Silane At high temperatures get gas phase reactions that produce rough, loosely adhering deposits and poor uniformity. At low temperatures deposition rates are to slow for industrial situations. Zone heating rear of furnace up to 15C hotter. (Better film uniformity) o Si APCVD 575 to 650 Toxic( 1 Atm but 90% N 2 ) Pyrophoric High Exposure Limit C o LPCVD 575 to 650C o

Silicon dioxide Low Temperature Loose adhering deposits on side walls of reactor. ( Particles that can contaminate the film. At high silane pressures allows for gas phase reactions. ( Promotes particle contamination and hazy films) Fair step coverage Low film density ( 2. 0 g/cm 3 ) Deposition rate complex function of Oxygen concentration Easy chemical reaction. ( Low activation energy, 0.4 ev (10 kcal/mole) ) Film depends on gas phase transport of material to surface Low temperature allows production of films that will serve as insulation between aluminum levels in device.

Si H H H H SiO 2 NO 650 to 750C Si O C C H H H H O O C H H C H H OCH 2 CH SilaneTetraethoxysilane TEOS SiO to 750C (LPCVD) 30 PA to 250 PA 100 to 1000 std. cc / min Medium Temperature

High Temperature Nonlinear pressure dependence that is function of wafer position. Small amounts of Chlorine in films that tends to cause cracking in a poly layer) Reagent depletion problems Phosphorus doping is difficult. ( The phosphorus oxides are volatile at high deposition temperatures.) Excellent Uniformity

Except for epi and parallel plate processes both sides of wafer are coated. Equipment Furnace with or without vacuum capability Plasma Chamber CVD is Crucial to Fabrication of IC's, Especially MOSFETS (The Bottom Line) Pad Silicon Dioxide First Monolayer of Silicon Nitride Si Cl N H H Precursor NHSiCl H H H H N H H H Si Cl H H Si Cl H H