ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Licensed Electrical & Mechanical Engineer Engineering 43 Chp 14-2 Op Amp Circuits

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Circuits  Introduce Two Very Important Practical Circuits Based On Operational Amplifiers  Recall the OpAmp  The “Ideal” Model That we Use R O = 0 R i = ∞ A v = ∞ BW = ∞  Consequences of Ideality R O = 0  v O = A v (v + − v − ) R i = ∞  i + = i − = 0 A v = ∞  v + = v − BW = ∞  OpAmp will follow the very Highest Frequency Inputs

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Ckt  Integrator  KCL At v − node  By Ideal OpAmp R i = ∞  i + = i − = 0 A v = ∞  v + = v − = 0 0   v

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Integrator cont  By the Ideal OpAmp Assumptions  Separating the Variables and Integrating Yields the Solution for v o (t)  A simple Differential Eqn  Thus the Output is a (negative) SCALED TIME INTEGRAL of the input Signal

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Ckt  Differentiator  By Ideal OpAmp v − = GND = 0V i − = 0  KCL at v − KVL  Now the KVL 0   v

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Differentiator cont.  Recall Ideal OpAmp Assumptions R i = ∞  i + = i − = 0 A v = ∞  v + = v − = 0  Then the KCL  Recall the Capacitor Integral Law  Thus the KVL  Multiply Eqn by C 1, then Take the Time Derivative of the new Eqn

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Differentiator cont  In the Previous Differential Eqn use KCL to sub v O for i 1 Using  Examination of this Eqn Reveals That if R 1 were ZERO, Then v O would be Proportional to the TIME DERIVATIVE of the input Signal In Practice An Ideal Differentiator Amplifies Electrical Noise And Does Not Operate well The Resistor R 1 Introduces a Filtering Action. –Its Value Is Kept As Small As Possible To Approximate a Differentiator

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Aside → Electrical Noise  ALL electrical signals are corrupted by external, uncontrollable and often unmeasurable, signals. These undesired signals are referred to as NOISE  The Signal-To-Noise Ratio  Simple Model For A Noisy 1V, 60Hz Sinusoid Corrupted With One MicroVolt of 1GHz Interference SignalNoise  Use an Ideal Differentiator  The SN is Degraded Due to Hi-Frequency Noise SignalNoise

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Class Exercise  Ideal Differen.  Given Input v 1 (t) SAWTOOTH Wave  Let’s Turn on the Lites for 10 minutes for YOU to Differentiate  Given the IDEAL Differentiator Ckt and INPUT Signal  Find v o (t) over 0-10 ms  Recall the Differentiator Eqn R 1 = 0; Ideal ckt

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Differentiator Ex.  Given Input v 1 (t)  The Slope from 0-5 mS  For the Ideal Differentiator  Units Analysis

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Differentiator cont.  Derivative Scalar PreFactor  A Similar Analysis for 5-10 mS yields the Complete v O  Apply the Prefactor Against the INput Signal Time-Derivative (slope) InPutOutPut

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Integrator Example  Given Input v 1 (t) SQUARE Wave  For the Ideal Integrator  Units Analysis Again

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Integrator Ex. cont.  The Integration PreFactor  0<t<0.1 S v 1 (t) = 20 mV (Const)  Next Calculate the Area Under the Curve to Determine the Voltage Level At the Break Points  0.1  t<0.2 S v 1 (t) = –20 mV (Const)  Integrate In Similar Fashion over 0.2  t<0.3 S 0.3  t<0.4 S

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis RC OpAmp Integrator Ex. cont.1  Apply the 1000/S PreFactor and Plot Piece-Wise

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Design Example  Design an OpAmp ckt to implement in HARDWARE this Math Relation  Examine the Reln to find an Integrator Summer

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Design Example  The Proposed Solution  The by Ideal OpAmps & KCL & KVL & Superposition

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Design Example  Then the Design Eqns  The Ckt Eqn  TWO Eqns in FIVE unknowns  This means that we, as ckt designers, get to PICK 3 values  For 1 st Cut Choose C = 20 μF R 1 = 100 kΩ R 4 = 20 kΩ

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Design Example  In the Design Eqns  If the voltages are <10V, then all currents should be the in mA range, which should prevent over-heating 20μ 100k 20k 10k 20k  Then the DESIGN

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis LM741 OpAmp Schematic

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Some LM741 Specs

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis OpAmp Frequency Response  The Ideal OpAmp has infinite Band- Width so NO Matter how FAST the input signals  However, REAL OpAmps Can NOT Keep up with very fast signals The Open Loop Gain, A O, starts to degrade with increasing input frequencies

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 22 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Gain∙BandWidth for LM741 −20db/Decade Slope The Unity Gain Frequency, f t, is the BandWidth Spec

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 23 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis BandWidth Limit Implications  Recall the OpAmp based Inverting ckt  The NONideal Analysis yielded  Noting That All the R’s are Constant; Rewrite above as  For Very Large A

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 24 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis BandWidth Limit Implications  As Frequency Increases the Open- Loop gain, A, declines so the Limit does NOT hold in:  If  Then the Denom in the above Eqn ≠ 1  Thus significantly smaller A DECREASES the Ideal gain  For Typical Values of the R’s the Open- Loop Gain, A, becomes important when A is on the order of about 1000

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 25 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Gain∙BandWidth for LM741  Frequency significantly degrades Amplification Performance for Source Frequencies > 10 kHz

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 26 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Voltage Swing Limitations  Real OpAmps Can NOT deliver Unlimited Voltage- Magnitude Output  Recall the LM741 Spec Sheet that show a Voltage Output Swing of about ±15V For Source Voltages of ±20 V  If the Circuit Analysis Predicts v o of more than the Swing, the output will be “Clipped”  Consider the Inverting Circuit:

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 27 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Vswing Clipping  Since the Real OutPut can NOT exceed 15V, the cosine wave OutPut is “Clipped Off” at the Swing Spec of 15V ENGR43_Lec14b_OpAmp_V_Swing_Plot_1204.m

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 28 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Short-Ckt Current Limitations  Real OpAmps Can NOT deliver Unlimited Current- Magnitude Output  Recall the LM741 Spec Sheet that shows an Output Short Circuit Current of about 25mA  If the Circuit Analysis Predicts i o of more than This Current, the output will also be “Clipped”  Consider the Inverting Circuit:

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 29 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Current Saturation  Since the Real OutPut can NOT exceed 25mA, the cosine wave OutPut is “Clipped Off” at the Short Circuit Current spec of 25mA ENGR43_Lec14b_OpAmp_Current_Saturation_ Plot_1204.m

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 30 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Slew Rate = dv o /dt  For a Real OpAmp we expect the OutPut Cannot Rise or Fall Infinitely Fast.  This Rise/Fall Speed is quantified as the “Slew Rate”, SR  Mathematically the Slew Rate limitation  The 741 Specs indicate a Slew Rate of

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 31 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Slew Rate = dv o /dt  If dv in /dt exceeds the SR at any point in time, then the output will NOT be Faithful to input The OpAmp can NOT “Keep Up” with the Input  Consider the Example at Top Right  Then the Time Slope of the Source

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 32 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Slew Rate = dv o /dt  The Maximum value of dv S /dt Occurs at t=0. Compare the max to the SR  Thus the source Rises & Falls Faster than the SR  When the Source Slope exceeds the SR the OpAmp Output Rises/Falls at the SR This produces a STRAIGHT-LINE output with a slope of the SR when the source rises/falls Faster than the SR until the OpAmp “Catches Up” with the Ideal OutPut

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 33 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Slew Rate = dv o /dt

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 34 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Full Power BandWidth  The Full Power BW is the Maximum Frequency that the OpAmp can Deliver an Undistorted Sinusoidal Signal The Quantity, f FP, is limited by the SLEW RATE  Determine This Metric for the LM741  The 741 has a max output, V om, of ±12V  Applying a sinusoid to the input find at full OutPut power (Full Output Voltage)  Recall the Slew Rate

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 35 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Full Power BandWidth  Taking d/dt of the OpAmp running at Full Output  Thus the maximum output change-rate (slope) in magnitude  Recall ω = 2πf  Setting |dv o /dt| max = to the Slew Rate

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 36 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Full Power BandWidth  Isolating f in the last expression yields f FP :  From the LM741 Spec Sheet SR = 0.5 V/µS |V omax | min = 12V  Then f FP :

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 37 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Full Power BandWidth  Thus the 741 OpAmp can deliver UNdistorted, Full Voltage, sinusoidal Output (±12V) for input Frequencies up to about 6.63 kHz

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 38 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work  Let’s Work These Probs  Choose C Such That Find Energy Stored on Cx

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 39 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis All Done for Today OpAmp Circuit Design

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 40 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical & Mechanical Engineer Engineering 43 Appendix

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 41 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 42 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 43 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 44 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 45 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 46 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Practical Example  Simple Circuit Model For a Dynamic Random Access Memory Cell (DRAM)  Also Note the TINY Value of the Cell-State Capacitance (50x F)  Note How Undesired Current Leakage is Modeled as an I-Src

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 47 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Practical Example cont  The Criteria for a Logic “1” V cell >1.5 V  Now Recall that V = Q/C Or in terms of Current  During a WRITE Cycle the Cell Cap is Charged to 3V for a Logic-1 Thus The TIME PERIOD that the cell can HOLD the Logic-1 value  Now Can Calculate the DRAM “Refresh Rate”

ENGR-43_Lec-14a_IDeal_Op_Amps.pptx 48 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Practical Example cont.2  Consider the Cell at the Beginning of a READ Operation  Then The Output  Calc the Best-Case Change in V I/O at the READ  When the Switch is Connected Have Caps in Parallel