Engineering 100 Section 250 Combinational Logic -- Examples 9/13/2010
Truth table ABCOut
Truth table ABCOut
NOT module NOT( input wire A, output reg B); begin if (A == 1'b0) begin B = 1'b1; end else begin B = 1'b0; end endmodule
module RR_raise10( input wire OSU, input wire Bowl, output reg raise1, output reg raise0); begin raise1 = 1'b0; raise0 = 1'b0; if (OSU == 1'b0 && Bowl == 1'b1) begin raise1 = 1'b0; raise0 = 1'b1; end else if (OSU == 1'b1 && Bowl == 1'b0) begin raise1 = 1'b0; raise0 = 1'b1; end else if (OSU == 1'b1 && Bowl == 1'b1) begin raise1 = 1'b1; raise0 = 1'b1; end endmodule
module add( input wire [1:0] A, input wire [1:0] B, output reg [2:0] C); begin C[2:0] = A[1:0] + B[1:0]; end endmodule Add
Bad Add module add( input wire [1:0] A, input wire [1:0] B, output reg [1:0] C); begin if ( A == 2'b00 && B == 2'b00) begin C = 3'b000; end else if ( A == 2'b00 && B == 2'b01) begin C = 3'b001;... end else if ( A == 2'b11 && B == 2'b10) begin C = 3'b101; end else begin C = 3'b110; end endmodule
Truth table ABC