The Xilinx Spartan 3 FPGA EGRE 631 2/2/09

Basic types of FPGA’s One time programmable Reprogrammable (non-volatile) –Retains program when powered down SRAM-based reprogramable –Must be reprogrammed each time powered up –This is usually accomplished by using a small serial PROM.

Spartan-3 Architecture Fundamental Elements Configurable Logic Blocks (CLBs) –Consists of RAM based look up table to implement logic and storage elements that can be used as flip-flops or latches. Input Output Blocks (IOBs) –Controls the flow of data between IO pins and internal logic. Supports many different signal standards. (Tri- state, bidirectional, LVTTL, etc. Block RAM (BRAM) 18 bit Multiplier Blocks Digital Clock Manager (DCM)

CLB’s

Spartan 3 Configurable Logic Blocks (CLB’s) CLBs contain Ram based lookup tables to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logic functions as well as store data.

Spartan 3E IO Blocks (IOB’s) IOB’s control flow of data between IO pins and the internal logic. Each IOB supports bidirectional data flow, 3-state operation, and numerous different signal standards. (We will typically use LVTTL). See data sheet.

I/O block

I/O block continued

CLB’s – four slices per CLB

Slices and CLBs Each Spartan  -III CLB contains four slices –Local routing provides feedback between slices in the same CLB, and it provides routing to neighboring CLBs –A switch matrix provides access to general routing resources CIN Switch Matrix BUFT COUT Slice S0 Slice S1 Local Routing Slice S2 Slice S3 CIN SHIFT

Slice 0 LUT Carry LUT Carry DQ CE PRE CLR D Q CE PRE CLR Simplified Slice Structure Each slice has four outputs –Two registered outputs, two non-registered outputs –Two BUFTs associated with each CLB, accessible by all 16 CLB outputs Carry logic runs vertically, up only –Two independent carry chains per CLB

Detailed Slice Structure The next few slides discuss the slice features –LUTs –MUXF5, MUXF6, MUXF7, MUXF8 (only the F5 and F6 MUX are shown in this diagram) –Carry Logic –MULT_ANDs –Sequential Elements

Combinatorial Logic A B C D Z Look-Up Tables Combinatorial logic is stored in Look-Up Tables (LUTs) –Also called Function Generators (FGs) –Capacity is limited by the number of inputs, not by the complexity Delay through the LUT is constant ABCDZ

Connecting Look-Up Tables F5 F8 F5 F6 CLB Slice S3 Slice S2 Slice S0 Slice S1 F5 F7 F5 F6 MUXF8 combines the two MUXF7 outputs (from the CLB above or below) MUXF6 combines slices S2 and S3 MUXF7 combines the two MUXF6 outputs MUXF6 combines slices S0 and S1 MUXF5 combines LUTs in each slice

Fast Carry Logic Simple, fast, and complete arithmetic Logic –Dedicated XOR gate for single-level sum completion –Uses dedicated routing resources –All synthesis tools can infer carry logic

CO DICI S LUT CY_MUX CY_XOR MULT_AND A B A x B LUT MULT_AND Gate Highly efficient multiply and add implementation –Earlier FPGA architectures require two LUTs per bit to perform the multiplication and addition –The MULT_AND gate enables an area reduction by performing the multiply and the add in one LUT per bit

Distributed SelectRAM Resources Uses a LUT in a slice as memory Synchronous write Asynchronous read –Accompanying flip-flops can be used to create synchronous read RAM and ROM are initialized during configuration –Data can be written to RAM after configuration Emulated dual-port RAM –One read/write port –One read-only port RAM16X1S O D WE WCLK A0 A1 A2 A3 LUT RAM32X1S O D WE WCLK A0 A1 A2 A3 A4 RAM16X1D SPO D WE WCLK A0 A1 A2 A3 DPRA0DPO DPRA1 DPRA2 DPRA3 Slice LUT

Block SelectRAM Resources Up to 3.5 Mb of RAM in 18- kb blocks –Synchronous read and write True dual-port memory –Each port has synchronous read and write capability –Different clocks for each port Supports initial values Synchronous reset on output latches Supports parity bits –One parity bit per eight data bits DIA DIPA ADDRA WEA ENA SSRA CLKA DIB DIPB WEB ADDRB ENB SSRB DOA CLKB DOPA DOPB DOB 18-kb block SelectRAM memory

ConfigurationDepthData BitsParity Bits 16k x 116 kb10 8k x 28 kb20 4k x 44 kb40 2k x 92 kb81 1k x 181 kb x Dual-Port Block RAM Configurations Configurations available on each port Independent configurations on ports A and B –Supports data-width conversion, including parity bits Port A: 8 bits IN 8 bit OUT 32 bit Port B: 32 bits

Dedicated Multiplier Blocks 18-bit twos complement signed operation Optimized to implement Multiply and Accumulate functions Multipliers are physically located next to block SelectRAM™ memory 18 x 18 Multiplier 18 x 18 Multiplier Output (36 bits) Data_A (18 bits) Data_B (18 bits) 4 x 4 signed 8 x 8 signed 12 x 12 signed 18 x 18 signed

Spartan-3A FPGA Starter Kit board User Guide Spartan III Starter –Kit