Summer Research Progress: Week 2 – DSP vs FPGA

Slides:



Advertisements
Similar presentations
Sundanc e High-tech DSP solutions. Giving you the freedom to design Multiprocessor Technology Ltd SOFTWARE UTILITY TOOLS.
Advertisements

© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
Reconfigurable Computing (EN2911X, Fall07) Lecture 04: Programmable Logic Technology (2/3) Prof. Sherief Reda Division of Engineering, Brown University.
StreamBlade SOE TM Initial StreamBlade TM Stream Offload Engine (SOE) Single Board Computer SOE-4-PCI Rev 1.2.
Slides created by: Professor Ian G. Harris PIC Development Environment MPLAB IDE integrates all of the tools that we will use 1.Project Manager -Groups.
Software Defined Radio
DSP Algorithm on System on Chip Performed by : Einat Tevel Supervisor : Isaschar Walter Accompanying engineers : Emilia Burlak, Golan Inbar Technion -
Preliminary Design Review Jan 31, 2006 Brianna Bethel Robert Havlik Jessica Lowry Alex Silva.
Configurable System-on-Chip: Xilinx EDK
FPGA BASED IMAGE PROCESSING Texas A&M University / Prairie View A&M University Over the past few decades, the improvements from machine language to objected.
Kabuki 2800 Critical Design Review 19 October 2006.
1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.
Programmable System on Chip Fully Configurable Mixed Signal Array Allows for Completely Customizable System Designs Capable of Internal MCU.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
v8.2 System Generator Audio Quick Start
111 Development Tools for ARM-Powered Devices Name of presenter RealView Microcontroller Development Kit ULINK2 USB/JTAG Adapter Evaluation Boards.
FPGA-Based Systems Design Flow in Action By: Ramtin Raji Kermani.
Microcontroller: Introduction
Face-Recognition In Intelligent Sureillence System Feng Zhao 2007 Nov.
Engineering 1040: Mechanisms & Electric Circuits Fall 2011 Introduction to Embedded Systems.
Detailed Technical Feature Presentation Background Information The Importance of Software Software Roadblocks Development Environment DSP Development Cycle.
GallagherP188/MAPLD20041 Accelerating DSP Algorithms Using FPGAs Sean Gallagher DSP Specialist Xilinx Inc.
Getting Started With DSP A. What is DSP? B. Which TI DSP do I use? Highest performance C6000 Most power efficient C5000 Control optimized C2000 TMS320C6000™
FPGA Based Fuzzy Logic Controller for Semi- Active Suspensions Aws Abu-Khudhair.
Keil Products in a Single Slide
Dr. Sanatan Chattopadhyay Dr. Sudipta Bandopahyaya
© 2011 Xilinx, Inc. All Rights Reserved Intro to System Generator This material exempt per Department of Commerce license exception TSU.
Dr. Konstantinos Tatas ACOE201 – Computer Architecture I – Laboratory Exercises Background and Introduction.
Programmable Logic- How do they do that? 1/16/2015 Warren Miller Class 5: Software Tools and More 1.
CPE 169 Digital Design Laboratory Digilent Inc. Nexys Development Board.
The World Leader in High Performance Signal Processing Solutions Low Cost JTAG Emulator for Blackfin® Processors.
The 6713 DSP Starter Kit (DSK) is a low-cost platform which lets customers evaluate and develop applications for the Texas Instruments C67X DSP family.
W.Skulski Phobos Workshop April /2003 Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University.
© 2002 The MathWorks, Inc. September 2002 Advanced Embedded Tool capabilities for Texas Instruments DSPs © 2002 The MathWorks, Inc. David Hilf Third Party.
Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.
Lecture #3 Page 1 ECE 4110– Sequential Logic Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.No Class Monday, Labor Day Holiday 2.HW#2 assigned.
Digital Radio Receiver Amit Mane System Engineer.
MOI PROJECT Gugulethu Mabuza Bachelor Science Electrical Engineering Michigan State University.
Arduino. What is it? A open-source software suite and single-board microcontroller. Allows easy and affordable prototyping of microcontroller applications.
Concept of Modular Design Module Carriers Embedded or PC-Host Modules A/D,D/A,I/O DSP,FPGA IMAGING,MEMORY Systems Data Acquisition Medical Industrial Control.
Xilinx Programmable Logic Design Solutions Version 2.1i Designing the Industry’s First 2 Million Gate FPGA Drop-In 64 Bit / 66 MHz PCI Design.
Research on Reconfigurable Computing Using Impulse C Carmen Li Shen Mentor: Dr. Russell Duren February 1, 2008.
The Xilinx Spartan 3 FPGA EGRE 631 2/2/09. Basic types of FPGA’s One time programmable Reprogrammable (non-volatile) –Retains program when powered down.
FPGA (Field Programmable Gate Array): CLBs, Slices, and LUTs Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side.
SW and HW platforms for development of SDR systems SW: Model-Based Design and SDR HW: Concept of Modular Design and Solutions Fabio Ancona Sundance Italia.
Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.
Developing software and hardware in parallel Vladimir Rubanov ISP RAS.
© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU DSP Design Flow System Generator for DSP.
Working with Xilinx Spartan 3 Embedded Systems Lab 2009.
Lecture #3 Page 1 ECE 4110–5110 Digital System Design Lecture #3 Agenda 1.FPGA's 2.Lab Setup Announcements 1.HW#2 assigned Due.
Michael Neuberg Christopher Picard.  Encoders are used to determine the exact rotational position for elevation or azimuth of the radar dish  The encoders.
Presentation for: ILA October 16, 2007 Producing the next generation of Integrated GPS/eLoran Receivers Integrated eLoran/GPS Receiver Development Platform.
Introduction to the C6713 Laurier Boulianne
Embedded System. What is an Embedded System? Computing systems embedded within electronic devices Hard to define – Nearly any computing system other than.
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
Proposal for an Open Source Flash Failure Analysis Platform (FLAP) By Michael Tomer, Cory Shirts, SzeHsiang Harper, Jake Johns
Software Toolchains. Instructor: G. Rudolph, Summer Motivation Desktop Programmers typically write code on the same kind of machine on which it.
Introduction to VHDL Coding Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.
Introduction to Labs Wenchao Cao, Teaching Assistant Department of EECS University of Tennessee.
Peter JansweijerATLAS week: February 24, 2004Slide 1 Preparatory Design Studies MROD-X Use Xilinx Virtex II Pro –RocketIO –PowerPC –Port the current MROD-In.
Bob Hirosky L2  eta Review 26-APR-01 L2  eta Introduction L2  etas – a stable source of processing power for DØ Level2 Goals: Commercial (replaceable)
Software Toolchains. Motivation 2 Write Run Edit, compile, link, run, debug same platform Desktop Write Run Edit, compile, link, debug on host; run on.
A Brief Introduction to FPGAs
FPGA Technology Overview Carl Lebsack * Some slides are from the “Programmable Logic” lecture slides by Dr. Morris Chang.
CEng3361/18 CENG 336 INT. TO EMBEDDED SYSTEMS DEVELOPMENT Spring 2007 Recitation 01.
PROGRAMMABLE LOGIC CONTROLLERS SINGLE CHIP COMPUTER
ECE 4110–5110 Digital System Design
Using FPGAs with Processors in YOUR Designs
ریز پردازنده. ریز پردازنده مراجع درس میکروکنترلرهای AVR برنامه نویسی اسمبلی و C محمدعلی مزیدی، سپهر نعیمی و سرمد نعیمی مرجع کامل میکروکنترلرهای AVR.
The performance requirements for DSP applications continue to grow and the traditional solutions do not adequately address this new challenge Paradigm.
Presentation transcript:

Summer Research Progress: Week 2 – DSP vs FPGA Ross Keyes, Ajo Maret Department of Electrical and Computer Engineering Temple University URL: 1

FPGA Specifications Spartan - 3A Family: Very low cost, high-performance logic solution for high-volume consumer-oriented applications. Up to 519 I/O pins. 622+ Mb/s data transfer rate per I/O. DDR/DDR2 SDRAM support up to 400 Mb/s Programmable input delays for finer timing control. Up to 373 Kbits of efficient distributed RAM IEEE1149.1/1532JTAG programming/debug port Wide frequency range (5 MHz to over 300 MHz) Complete Xilinx ISE and WebPACK development system support Fully compliant 32-/64-bit 66 MHz PCI support

Design Flow (FPGA) Hardware in the loop Binary Data Binary Data MATLAB Simulink & SysGen Simulink & SysGen FPGA

FPGA software Xilinx ISE Design Suit 11.1 The ISE Design Suite 11.1 sets new industry standard for delivering FPGA design tools and intellectual property to embedded, DSP and logic designers. In our case we use a specific Xilinx Design Tool-kit known as the DSP Tool-kit which comprises of the System Generator (Simulink) The XtremeDSP Starter Kit – Spartan 3A DSP Edition cost from $600- $2000+

Sample Code (Matlab Code):

System Generator (Simulink) Flow-Diagram:

DSP Specifications Chip: Fabricated on 0.09 µm technology. Can operate at up to 120 MHz Can use as low as 0.14 mW/MHz 320 KB RAM built in Pins: 196 Board: Embedded USB XDS100 JTAG emulator TI TLV320AIC3204C Stereo Codec (stereo in, headphone out) 512K-bit EEPROM

Process is similar to running on a microprocessor. Design Flow (DSP) Process is similar to running on a microprocessor. Binary Data Binary Data DSP C Code

DSP software TI Code Composer Studio v4 Based on the Eclipse IDE Built in C compiler Full version is free as long a board with the USB XDS100 JTAG emulator is being used (software would normally cost $1895) Can single step through DSP assembly code as well as C code.

Software Issues The Xilinx ISE software that includes System Generator is very bulky. Downloading and extracting the software takes hours. Installing software also takes hours. Each version of System Generator will only work with two or three versions of MATLAB Fortunately Dr. Silage had extra Xilinx licenses that he was willing to spare.