1/1/ / faculty of Electrical Engineering eindhoven university of technology Input/Output devices Part 3: Programmable I/O and DSP's dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

1/1/ / faculty of Electrical Engineering eindhoven university of technology Programmable input/output controllers Many I/O control tasks can be done in software, using simple parallel ports and timers –Keyboard scanning and encoding –Simple motor control –Pulse counting for position encoding –Other non-standard low speed (but time-critical) tasks Don’t use main processor for this ‘simple’ stuff ! Use programmable I/O controllers here: modified single-chip microcomputers

1/1/ / faculty of Electrical Engineering eindhoven university of technology The Intel 8042 ‘slave processor’ 8042 data read write address chip select DMA req. DMA ack. output full (not) input full 8048 CPU 2KB program 128B data master CPU interface 8 bits timer 8 bit parr. I/O 8 bit parr. I/O int inputs ! interrupt requests Original 8048: external data bus interface and I/O port

1/1/ / faculty of Electrical Engineering eindhoven university of technology data output register status register input full output full flag 0 flag 1 set 'out dbb,a' load read status external data bus data input register The 8042 'master CPU interface' –Flag 0 (and 4 other status reg. bits) are ‘user defined’ read data res write data/cmmd load internal data bus input full pin output full pin internal interrupt 'clear/complement/jump f0' 'clear/complement/jump f1' set s/r 'in a,dbb' res copy of addres s input

1/1/ / faculty of Electrical Engineering eindhoven university of technology The Z8090 Universal Peripheral Controller Based upon the Zilog Z8 microcomputer –8 bits CPU, 2 KB program ROM, 256 byte data RAM –Memory mapped I/O includes timers and parr. ports Master CPU interface differs a lot from 8042 –Master reads/writes 16 byte ‘window’ in data RAM window location controlled by Z8090 program –Simple form of DMA to/from data RAM start and end locations controlled by Z8090 program –Z8090 interrupts master by setting output bit –Master interrupts Z8090 by dummy write action

1/1/ / faculty of Electrical Engineering eindhoven university of technology Special purpose co-processors (1) Relatively simple co-processors with a special data path can beat complex standard processors ! Co-processors for standard algorithms exist Data encryption and decryption DES and RSA devices are available. Separate devices are preferred because of security reasons ! Data compression and expansion Image (CCITT FAX, JPEG, MPEG) and data file (LZW = ‘ZIP’) (de-)compression devices exist

1/1/ / faculty of Electrical Engineering eindhoven university of technology Special purpose co-processors (2) Parametrisation is possible with writable ‘constants’ and programmable sequencing logic Fast Fourier Transform devices have programmable address generators and multiplication ‘constants’ (In ‑ )Finite Impulse Response filters are parametrised in the same way to generate different characteristics 2-D graphics image filter devices are more of the same Used for noise reduction, smoothing Edge detection, sharpening, contrast enhancement Removing distortions and blurr (very complex!)

1/1/ / faculty of Electrical Engineering eindhoven university of technology Digital Signal Processing Lots of Digital Signal Processors (DSP's) have been designed for digital filtering operations     l i iinn Cinout 0 )( Finite Impulse Response filter –One output requires l adds and (l + 1) multiplications –The last l input values must be remembered and an array of (l + 1) constants must be available somewhere DSP = multiply-add datapath + >1 memory + loop addressing

1/1/ / faculty of Electrical Engineering eindhoven university of technology Digital Signal Processors Support standard CPU operations: more general purpose than FIR/IIR filter devices ! –They can take decisions based upon the filtered values and switch between different filter characteristics Needed for, for instance, telephone line modems –They can be programmed for 'strange' input value addressing schemes Like used in two-dimensional image filtering

1/1/ / faculty of Electrical Engineering eindhoven university of technology High performance DSP’s: parallel Multiple on-chip memories with parallel access using independent data and address buses Multiple I/O interfaces use DMA to read/write the memories in parallel to calculations Programmable address generators running in parallel to actual multiply/add datapath Actual calculations use floating point for a wider 'dynamic range' and lower digital output noise

1/1/ / faculty of Electrical Engineering eindhoven university of technology The ultimate in DSP’s: real-time video Need on the order of 1 billion operations/second for 3-D picture generation or video filtering Intel’s Multi-Media eXtension (MMX): 8 identical byte operations with one instruction Texas Instrument’s 32080: 5 processors (w. ‘MMX’) and 25 memories on one chip Philips’ TriMedia: 5 ‘MMX’-like instructions in one super- instruction