Sept. 2005 EE24C Digital Electronics Project Design of a Digital Alarm Clock.

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Presentation transcript:

Sept EE24C Digital Electronics Project Design of a Digital Alarm Clock

Sept EE24C Digital Electronics Project Contents Natural Specification Design Specification Labs Description Theory : –Sequential Logic Design –Counters and Registers Design Solution Material Resources

Sept EE24C Digital Electronics Project Natural Specification (From a Hardware Store Owner) "I’m proposing a 2-month contract to a second year Electrical and Computer Eng. student. The elected student will have to develop for the local market a digital clock that displays time, i.e. 2:00:00 AM. The device should have features such as time setting, alarm setting, autonomy of 3 hours in case of power failure, and proper time display using 7-segment Leds."

Sept EE24C Digital Electronics Project From the previous specification, a good design approach consists of analyzing the system in terms of its functionality(block diagrams) and electrical properties. For this design we will use an FPGA board as the target architecture and Xiinx ISE/Modelsim as the software development platform. We consider the following steps which are crucial for the project completion: Modular analysis and implementation of the system. Analysis of electrical properties (power consumption, operating frequency, size on chip). Implementation and testing of the final design. Writing of a small user manual to be included in your project report.

Sept EE24C Digital Electronics Project Design Specification The system is synchronous and reactive1. It uses a reference clock of 50 MHz in order to generate other useful signals for its internal operations. We can identify four major functions: Commands entering via a 4 x 3 keypad which is used for setting purposes. Counting module made of four BCD counters which modulo are 2, 12(counting from 1 to 11), 60, and 60 respectively. FSM controller that is used for the sequencing of events. Time-multiplexing display of the correct time (i.e 2:30:58 am).

Sept EE24C Digital Electronics Project Figure 1: Block diagram of the digital alarm clock

Sept EE24C Digital Electronics Project Figure 2: Controller and alarm modules

Sept EE24C Digital Electronics Project Figure 3: Alarm module

Sept EE24C Digital Electronics Project - Lab 1: Design of Modulo counters - Lab 2: Debounce-free Keypad Encoder and Time-multiplexing Display Decoder - Lab 3 Frequency Divider and Alarm Module - Lab 4: Buzzer module and Power Failure Detection - Lab 5: FSM Controller Module - Project Realization: Integration and Testing

Sept EE24C Digital Electronics Project Lab 1: Design of Modulo Counters

Sept EE24C Digital Electronics Project Basic element to be used

Sept EE24C Digital Electronics Project

Sept EE24C Digital Electronics Project

Sept EE24C Digital Electronics Project Figure 7: Counting Module’s Block Diagram

Sept EE24C Digital Electronics Project Lab 2: Keypad Encoder and Time-multiplexing Display Decoder Debounce-free Keypad Encoder

Sept EE24C Digital Electronics Project