-1- UC San Diego / VLSI CAD Laboratory Methodology for Electromigration Signoff in the Presence of Adaptive Voltage Scaling Wei-Ting Jonas Chan, Andrew B. Kahng and Siddhartha Nath VLSI CAD LABORATORY, UC San Diego

-2- Outline Motivation Motivation Previous Work Previous Work Analysis Models Analysis Models Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-3- Bias Temperature Instability (BTI) |ΔV th | increases when device is on (stressed) |ΔV th | is partially recovered when device is off (relaxed) Device aging (|ΔV th |) accumulates over time NBTI: PMOS PBTI: NMOS |V gs | time ONOFF ONOFF [VattikondaWC06]

-4- Electromigration in Interconnects Electromigration (EM) is the gradual displacement of metal atoms in an interconnect Electromigration (EM) is the gradual displacement of metal atoms in an interconnect I avg causes DC EM and affects power delivery networks I avg causes DC EM and affects power delivery networks I rms causes AC EM and affects clock and logic signals I rms causes AC EM and affects clock and logic signals

-5- Adaptive Voltage Scaling (AVS) Accumulated BTI  higher |ΔV th |  slower circuit Accumulated BTI  higher |ΔV th |  slower circuit AVS can compensate for performance degradation AVS can compensate for performance degradation Circuit Closed-loop AVS On-chip aging monitor Circuit performance Voltage regulator Circuit performance Vdd time Without AVS With AVS target

-6- BTI + AVS Signoff V lib V BTI Derated library |Vt||Vt| Circuit implementation and signoff netlist BTI degradation and AVS V final ? Step 1Step 2Step 3 Signoff loop of BTI Ensure circuit meets timing requirements under BTI aging Ensure circuit meets timing requirements under BTI aging Use AVS to offset BTI degradation Use AVS to offset BTI degradation

-7- EM + BTI + AVS Signoff? Stress on Wires V final Design Implementation V lib, V BTI Derated Libraries Signoff loop of BTI + EM Aggressive AVS scheduling results in more severe degradation Aggressive AVS scheduling results in more severe degradation Guardband during implementation increases due to degradation Guardband during implementation increases due to degradation How to signoff for EM with AVS? How to signoff for EM with AVS? What are area, power costs? What are area, power costs? What is the impact to EM lifetime? What is the impact to EM lifetime? BTI loop EM loop

-8- Outline Motivation Motivation Previous Work Previous Work Analysis Models Analysis Models Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-9- Previous Works EM lifetime and wire degradation models EM lifetime and wire degradation models –Closed-form lifetime models (Black, Arnaud et al., Federspiel et al.) –Statistical model for wire degradation (Mishra et al.) Claim their model reduces pessimism in Black’s Equation Claim their model reduces pessimism in Black’s Equation EM-durable circuits EM-durable circuits –Wire-sizing algorithms (Adler et al., Jiang et al.) –Wire segmentation and via insertion algorithms (Li et al.) –Current-aware routers (Lienig et al., Yan et al.) BTI Signoff BTI Signoff –Interactions between AVS and BTI (Chan et al., Chen et al., Basoglu et al.) No studies on three-way interactions between BTI, EM and AVS!!!

-10- Outline Motivation Motivation Previous Work Previous Work Analysis Models Analysis Models Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-11- EM Model: Black’s Equation t 50 – median time to failure (= log e 2 x MTTF) t 50 – median time to failure (= log e 2 x MTTF) A* – geometry-dependent constant A* – geometry-dependent constant J – current density in interconnect segment J – current density in interconnect segment n – constant ( = 2) n – constant ( = 2) E a – activation energy of metal atoms E a – activation energy of metal atoms k – Boltzmann’s constant k – Boltzmann’s constant T – temperature of the interconnect T – temperature of the interconnect EM degrades interconnect lifetime EM degrades interconnect lifetime Black’s Equation calculates lifetime of interconnect segment due to EM degradation Black’s Equation calculates lifetime of interconnect segment due to EM degradation

-12- New EM Model: Mishra-Sapatnekar Models resistance increase due to voids in wires instead of MTTF Models resistance increase due to voids in wires instead of MTTF Derived from statistical model of nucleation and growth time Derived from statistical model of nucleation and growth time Log-normal distribution

-13- New EM Model: Impact on Signal Wires Sweep different gate sizes up to 8× Sweep different gate sizes up to 8× Larger gates do not necessarily help to reduce EM impact Larger gates do not necessarily help to reduce EM impact ∼ 8% delay degradation for buffers smaller than 4× when resistance increases to high values ( ∼ 146%) ∼ 8% delay degradation for buffers smaller than 4× when resistance increases to high values ( ∼ 146%) Statistical model is optimistic in predicting delay penalties

-14- New EM Model: Impact on Signal Wires Sweep FO4 capacitive load by factors {1.0×, 1.6×, 2.1×} Sweep FO4 capacitive load by factors {1.0×, 1.6×, 2.1×} EM slows down circuit performance due to EM slows down circuit performance due to  increased stage delay  increased output transition times Delay increases by ~35% with large resistance increase ~200%

-15- Outline Motivation Motivation Previous Work Previous Work Analysis Models Analysis Models Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-16- Experimental Setup Multiple implementations based on different signoff corners Multiple implementations based on different signoff corners AES and DMA designs from Opencores AES and DMA designs from Opencores 28nm foundry FDSOI technology 28nm foundry FDSOI technology Commercial tool-based SP&R flows Commercial tool-based SP&R flows Synopsys PrimeTime for timing analysis Synopsys PrimeTime for timing analysis Matlab for AVS simlulation with BTI and EM Matlab for AVS simlulation with BTI and EM

-17- AVS Signoff Corner Selection Impl# V lib (V)V min V max V min 0.98V0.97V0.96V0.95V V BTI (V)V min V max N/A0.98V0.97V0.96V0.95V Characterize different derated libraries against BTI Evaluate impact of library characterization V final is predicted by cell chains ahead of implementation Eight implementations 1 : V BTI = V lib = V min  Ignore AVS 2 : Most pessimistic derated library 3 : V BTI = V lib = V max  Extreme corner for AVS 4 : No derated library (reference) 5 : Sweep around V final 6 : V final by cell chain prediction [ChanCK13] 7 : Sweep around V final 8 : Sweep around V final

-18- AVS Signoff Corner Selection Optimistic about AVS Pessimistic about AVS

-19- AVS Impact on EM Lifetime V final (V) Assume no EM fix at signoff BTI degradation is checked at each step and MTTF is updated as 30% MTTF penalty 200mV voltage compensation

-20- Power Penalty to Fix EM with AVS Core power increases due to elevated voltage P/G power increases due to both elevated voltage and mesh degradation A tradeoff between invested guardband in signoff Highest invested guardband Least invested guardband 14% power penalty

-21- EM Impact on AVS Scheduling AVS behavior is an important role to decide the EM penalty on lifetime AVS behavior is an important role to decide the EM penalty on lifetime We empirically sweep AVS voltage step size to obtain the impact We empirically sweep AVS voltage step size to obtain the impact –#Implementation 3 is used –AVS starts at 0.9V, and no EM fix for AVS in signoff 5 step sizes 5 step sizes –S1 = 8mV –S2 = 10mV –S3 = 15mV –S4 = 18mV –S5 = 20mV

-22- EM Impact on AVS Scheduling 1.2 years MTTF penalty

-23- Outline Motivation Motivation Previous Work Previous Work Analysis Models Analysis Models Experimental Setup and Results Experimental Setup and Results Conclusions Conclusions

-24- Conclusions We study the joint impact of BTI, AVS and EM on signoff We study the joint impact of BTI, AVS and EM on signoff We study two EM models and their impact on implementation (i) Black’s Equation and (ii) Mishra- Sapatnekar We study two EM models and their impact on implementation (i) Black’s Equation and (ii) Mishra- Sapatnekar We demonstrate empirical results for lifetime, area and power penalty due to EM when AVS is involved We demonstrate empirical results for lifetime, area and power penalty due to EM when AVS is involved –Up to 30% lifetime penalty We demonstrate empirical results for power at different signoff corners We demonstrate empirical results for power at different signoff corners –Up to 14% power penalty Ongoing Ongoing –Improve accuracy of signoff using a temperature gradient –Learning-based modeling to quantify design costs of reliability

-25- Thank you!

-26- Backup

-27- EM Model: Mishra-Sapatnekar Log-normal distribution

-28- Study on EM Impact in AVS System V regulator Core (V DD domain) Mesh and ring ∆R PG (due to EM) Assume two types of degradation Assume two types of degradation IR drop due to power mesh degradation (∆R PG due to EM) Signal wire degradation due to EM Signal wire degradation due to EM