Princess Sumaya Univ. Computer Engineering Dept. Chapter 4:

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 1 / 57 Stored Program Architecture  Instruction Cycle ●Fetch an instruction from memory ●Decode the instruction ●Get the operands ●Execute the instruction  Where is the next instruction? Program Counter (PC) Instruction Pointer (IP)  Where is the operand? Instructions (Program) Operands (Data) Opcode Operands Binary Operand

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 2 / 57 CPU  Datapath  Control Unit Register File CU ALU

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 3 / 57 General-Purpose Register Organization R1 R2 R3 R4 R5 R6 R7 MUX ALU 3 x 8 Decoder D SEL A SEL B SEL OPR AB

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 4 / 57 General-Purpose Register Organization R1 R2 R3 R4 R5 R6 R7 MUX ALU 3 x 8 Decoder D SEL A SEL B SEL OPR AB Examples: OperationOPRA SEL B SEL D SEL R1 ← R2 − R3 R4 ← SHL R4

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 5 / 57 General-Purpose Register Organization Examples: OperationOPRA SEL B SEL D SEL R1 ← R2 − R R4 ← SHL R Instructions (Program) Operands (Data)

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 6 / 57 Memory Interface  Address / Data Buses  Read / Write Control  Bidirectional / Unidirectional Data Bus Read Write

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 7 / 57 Building a Datapath  Datapath Elements PC InstructionMemory Addr Data ALU Sel A Sel B Sel C LD Data A Data B Register File Data C Write a program & compile it. Where do you want to put it? Where is the first instruction? What comes out of memory? Where to perform operation? Where are the operands? Who well tell us which reg? Where to store result? Can we save this reg to mem? 32

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 8 / 57 Building a Datapath  Datapath Elements PC InstructionMemory Addr Data ALU DataMemory Addr Data Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 9 / 57 Building a Datapath PC InstructionMemory Addr Data ALU DataMemory Addr Data How can we read it back? Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 10 / 57 Building a Datapath PC InstructionMemory Addr Data ALU DataMemory Addr Data Finished executing instruction. Where is the next instruction? Why +4? MUX 4 Adder Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 11 / 57 Building a Datapath PC InstructionMemory Addr Data ALU 4 Adder How can we add “immediate”? What if it is negative? SignExtend Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 12 / 57 Building a Datapath PC InstructionMemory Addr Data ALU 4 Adder SignExtend MUX What about “JMP Rel Disp”? It can be positive or negative! Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 13 / 57 Building a Datapath PC 4 Addr Data SignExtend MUX InstructionMemory Shift Left 2 Adder Adder ALU Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 14 / 57 Building a Datapath PC 4 Addr Data SignExtend MUX InstructionMemory Shift Left 2 MUX Adder Adder ALU Why the shift? Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 15 / 57 Building a Datapath PC 4 Addr Data SignExtend MUX InstructionMemory Shift Left 2 MUX Adder Adder ALU Why not use ALU instead of another adder? Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 16 / 57 Cy, Z, etc Adding Control Signals to the Datapath PC 4 Addr Data SignExtend 0 00MUXMUX1100MUXMUX111 InstructionMemory Shift Left MUXMUX1100MUXMUX111 Adder Adder ALU Control Unit Opcode etc Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 17 / 57 Adding Control Signals to the Datapath PC 4 Addr Data SignExtend 0 00MUXMUX1100MUXMUX111 InstructionMemory Shift Left MUXMUX1100MUXMUX111 Adder Adder ALU Control Unit Sel A Sel B Sel C LD Data A Data B Register File Data C DataMemory Addr Data MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 18 / 57 A Simple Implementation Scheme  ALU Control ALU 32 4 ALU Cntrl Cy Z slt R1, R2, R3 Cy = 1  Carry from last adder Z = 1  The result = 0

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 19 / 57 A Simple Implementation Scheme  Instruction Format ●Arithmetic/Logic OpcodeOperand(s), Address, Code 0 6 RsRs RtRt RdRd ShiftFunct R d = R s Funct R t FunctALU OperationALU Cntrl Lines Add Subtract AND OR SLT0111 Example: R 5 = R 3 + R Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 20 / 57 A Simple Implementation Scheme  Instruction Format ●Move Immediate OpcodeOperand(s), Address, Code R t = Value Example: R 1 = RtRt Immediate (Lower) 16 bits (can be positive or negative)

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 21 / 57 A Simple Implementation Scheme  Instruction Format ●Load Memory OpcodeOperand(s), Address, Code 35 6 RsRs 5516 RtRt Address R t = M [R s + Addr] 32 bits16 bits (can be positive or negative) Example: R 6 = M [R 4 – 1 ]

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 22 / 57 A Simple Implementation Scheme  Instruction Format ●Store Memory OpcodeOperand(s), Address, Code 43 6 RsRs 5516 RtRt Address M [R s + Addr] = R t Example: M [R 7 – 2 ] = R

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 23 / 57 A Simple Implementation Scheme  Instruction Format ●JE Operation OpcodeOperand(s), Address, Code 4 6 RsRs 5516 RtRt Offset If R s = R t then PC = PC + 4*Addr Example: PC is already incremented

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 24 / 57 MUXMUXMUXMUX Final Datapath Design PC 4 DataMemory Addr Data SignExtend 0 00MUXMUX1100MUXMUX111 Addr Data 1 11MUXMUX0011MUXMUX000 InstructionMemory Shift Left MUXMUX1100MUXMUX111 Adder Adder ALU RsRs RtRt Offset, Addr, Immediate RtRt RdRd Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 25 / 57 Program Setup  Write a Program  Assemble it  Store it in Memory Example: A F F F F

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 26 / 57 Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem 0 ƮMƮM A (MOV R 1, 10) RsRs RtRt Immediate Reg A Sel 00 Data A Ʈ Reg 1 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Sign Ext 10 ALU Ʈ ALU 10 Data C Adder MUX 4 PC Adder Ʈ Adder Ʈ Reg

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 27 / 57 Datapath Operation  How Fast Can the Clock Be? CLK PC I-Mem 0 ƮMƮM A (MOV R 1, 10) Reg A Sel 00 Data A Ʈ Reg 1 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Sign Ext 10 ALU Ʈ ALU 10 Data C Adder MUX 4 PC Adder Ʈ clk Ʈ Reg

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 28 / 57 Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem (Add R 1,R 1,R 1 ) Reg A Sel 110 Data A 1 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 10 Data B 20 ALU 20 Data C Adder MUX 8 PC Adder RsRs RtRt FunctRdRd 10 Shift

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 29 / 57 Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C LD ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder 411– 1 RsRs RtRt Offset PC Adder 2 8 Adder MUX

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 30 / 57 Datapath Operation  How Fast Can the Clock Be? CLK PC I-Mem FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C LD ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder PC Adder 2 8 Adder MUX ƮMƮM Ʈ Reg Ʈ ALU

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 31 / 57 Datapath Operation  How Fast Can the Clock Be? CLK PC I-Mem FFFF (JE R 1,R 1,-1) Reg A Sel 120 Data A 1 Reg C Sel Reg C LD ALU MUX 6 (Sub) ALU Ctrl 20 Data B 0 ALU 12 PC Adder PC Adder 2 8 Adder MUX Ʈ Adder Ʈ clk Ʈ Reg Ʈ ALU ƮMƮM

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 32 / 57 Single-Cycle Implementation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC I-Mem i 8C (LD R 4,[R 3 +7]) RsRs RtRt Address Reg A Sel 3 d Data A 4 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 7 Sign Ext d +7 ALU v Data C D-Mem v

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 33 / 57 Single-Cycle Implementation  Clock Speed? CLK PC I-Mem i 8C (LD R 4,[R 3 +7]) Reg A Sel 3 d Data A 4 Reg C Sel Reg C LD ALU MUX 2 (Add) ALU Ctrl Mem MUX 7 Sign Ext d +7 ALU v Data C D-Mem v ƮMƮM Ʈ Reg Ʈ ALU Ʈ clk Ʈ Reg ƮMƮM

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 34 / 57 Single-Cycle Implementation Example: Ʈ M = 200 picoseconds Ʈ ALU = 100 picoseconds Ʈ Adder = 100 picoseconds Ʈ Reg = 50 picoseconds Fastest Clock? MOV/ALU: Ʈ clk > Ʈ M + 2 Ʈ Reg + Ʈ ALU Conditional Jump: Ʈ clk > Max Ʈ M + Ʈ Reg + Ʈ ALU Load Memory: Ʈ clk > 2 Ʈ M + 2 Ʈ Reg + Ʈ ALU Store Memory: Ʈ clk > 2 Ʈ M + Ʈ Reg + Ʈ ALU TypeDelay MOV / ALU400 ps LD600 ps ST550 ps Cond. Jump350 ps Ʈ clk = ps  GHz Max + Ʈ Adder Ʈ M Ʈ Adder

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 35 / 57 Multicycle Implementation  Instructions take different number of clock cycles  Functional units can be shared within the execution of a single instruction IR MDR X Y Result ALU Memory Addr Data PC Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 36 / 57 Multicycle Implementation  Some registers are not visible to the programmer IR MDR X Y Result ALU Memory Addr Data PC 4 SignExtend Shift Left 2 Exercise: Can you do all the previous instruction here? Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 37 / 57 Multicycle Implementation  Some registers are not visible to the programmer IR MDR X Y Result ALU Addr Data PC 4 SignExtend Shift Left Memory 01 Sel A Sel B Sel C LD Data A Data B Register File Data C

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 38 / 57 Multicycle Datapath Operation  Fetch Instruction CLK PC 0 ƮMƮM A Y MUX 2 (Add) ALU Ctrl PC MUX X MUX 4 ALU Ʈ ALU 0 IR LD Mem Rd PC LD Ʈ clk 1 IR Mem Out

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 39 / 57 Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands CLK PC A (MOV R 1, 10) RsRs RtRt Immediate Reg A Sel 0 X LD 0 Data A Ʈ Reg X 10 Sign Ext Ʈ clk IR LD Mem Rd IR Mem Out

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 40 / 57 Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC 4 IR A (MOV R 1, 10) RsRs RtRt Immediate 3 X 0 Y MUX ALU Ctrl X MUX ALU 2 2 (Add) 10 Ʈ ALU Result LD Result Ʈ clk X LD

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 41 / 57 Multicycle Datapath Operation  Fetch Instruction  Decode Instruction  Get Operands  Execute it CLK PC 4 IR A (MOV R 1, 10) RsRs RtRt Immediate 4 Result LD Result Ʈ clk 10 C MUX Reg C LD Ʈ Reg Ʈ clk > Max ƮMƮM Ʈ ALU Ʈ Reg Reg C Sel 1

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 42 / 57 Multicycle Datapath Operation CLK PC Mem Rd Mem Out IR LD IR ALU Ctrl ALU PC LD Reg A Sel Data A Sign Ext A A (MOV R 1, 10) 2 (Add) X LD X 10 0 Result LD Result 10 4 IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Rs R  X+IR[15:0] Immediate Reg[IR[20:16]]  R Rt RsRs RtRt Immediate 2 (Add) Reg C Sel 1 Reg C Write

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 43 / 57 Multicycle Datapath Operation CLK PC Mem Rd Mem Out IR LD IR ALU Ctrl ALU PC LD Reg A Sel Data A Sign Ext i Add result X LD X Result LD Result result i+4 IR  M[PC] PC  PC + 4 X  Reg[IR[25:21]] Y  Reg[IR[20:16]] R  PC+IR[16:0]] ALU Operation: R  X op Y R  X op IR[16:0] LD Operation: Reg[IR[20:16]]  MDR. Opcode Reg C Sel Rd Reg C Write i+4 instruction i+4+disp Add value Rs Selection Rs Reg[IR[15,11]]  R MDR  Mem[R] Mem[R]  Y Rt

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 44 / 57 Multicycle Implementation Example: Ʈ M = 200 picoseconds Ʈ ALU = 100 picoseconds Ʈ Adder = 100 picoseconds Ʈ Reg = 50 picoseconds Fastest Clock? Load Immediate/ALU: 4 Clocks Load Memory: 5 Clocks Store Memory: 4 Clocks TypeInstr. Mix LI / ALU52% LD25% ST10% Cond. Jump13% Ʈ clk = ps  GHz Conditional Jump: 3 Clocks

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 45 / 57 Control Implementation Control Unit CU Data Processing Unit DPU or Datapath Datapath Control Signals: ALU Operation, MUX Selection, Memory Rd/Wr, etc Datapath Control Signals: ALU Operation, MUX Selection, Memory Rd/Wr, etc Datapath Status Signals: IR Fields, ALU Flags Datapath Status Signals: IR Fields, ALU Flags

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 46 / 57 Control Implementation  Hardwired ●Standard Logic Components ●Fast ●Not Flexible, i.e. Difficult to Change Control Operation  Microprogrammed ●Memory-Based ●Speed Function of Memory (slower than hardwired) ●Flexible Design

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 47 / 57 Control Implementation  Hardwired ●Finite State Machine State Register Combinational Control Logic Datapath Control Outputs Datapath Control inputs

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 48 / 57 Microprogrammed Control Implementation  Each Line in the Micro- Program Executes Micro- Operations (in 1 Clock)  Fetch, Decode, Execute Cycle ALU Operation, MUX Selection, Memory Rd/Wr, etc

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 49 / 57 Microprogram Control Unit Datapath Control Signals:

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 50 / 57 Microprogram Control Unit C 19 C 0 1 Opcode Funct Z Cy etc Adder

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 51 / Microprogram Control Unit  Fetch Instruction μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 IR  M[PC], PC  PC + 4

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 52 / 57 Microprogram Control Unit  Decode / Get Operands IR  M[PC], PC  PC X  Reg[IR[25:21]], Y  Reg[IR[20:16]] SUB R, R, R Opcode = 0 Funct = = μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 53 / 57 Microprogram Control Unit  Execute Instruction IR  M[PC], PC  PC Res  X – Y = μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C SUB R, R, R Opcode = 0 Funct = X  Reg[IR[25:21]], Y  Reg[IR[20:16]]

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 54 / 57 Microprogram Control Unit  Execute Instruction Res  X – Y Reg[IR[15,11]]  Res = μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 SUB R, R, R Opcode = 0 Funct = IR  M[PC], PC  PC + 4 X  Reg[IR[25:21]], Y  Reg[IR[20:16]]

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 55 / 57 Microprogram Control Unit  Execute Instruction = μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 Res  X + Offset LD R, M[R+Adr] Opcode = 35 IR  M[PC], PC  PC + 4 X  Reg[IR[25:21]], Y  Reg[IR[20:16]]

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 56 / 57 Microprogram Control Unit  Execute Instruction = μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 MDR  M[Res] LD R, M[R+Adr] Opcode = 35 Res  X – Y IR  M[PC], PC  PC + 4 X  Reg[IR[25:21]], Y  Reg[IR[20:16]]

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. 57 / 57 Microprogram Control Unit  Execute Instruction = μPC M 0 S 1 S 0 C 19 C 18 C 17 C 16 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C Reg[IR[15,11]]  MDR MDR  M[Res] LD R, M[R+Adr] Opcode = 35 Res  X – Y IR  M[PC], PC  PC + 4 X  Reg[IR[25:21]], Y  Reg[IR[20:16]]

Princess Sumaya University – Computer Arch. & Org. (1) Computer Engineering Dept. Chapter 4