EE130/230A Discussion 13 Peng Zheng 1. Why New Transistor Structures? Off-state leakage (I OFF ) must be suppressed as L g is scaled down – allows for.

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Presentation transcript:

EE130/230A Discussion 13 Peng Zheng 1

Why New Transistor Structures? Off-state leakage (I OFF ) must be suppressed as L g is scaled down – allows for reductions in V T and hence V DD Leakage occurs in the region away from the channel surface  Let’s get rid of it! Drain Source Gate L g Thin-Body MOSFET: Buried Oxide Source Drain Gate Substrate “Silicon-on- Insulator” (SOI) Wafer 2

Thin-Body MOSFETs I OFF is suppressed by using an adequately thin body region. – Body doping can be eliminated  higher drive current due to higher carrier mobility Ultra-Thin Body (UTB) Buried Oxide Substrate Source Drain Gate T Si L g T Si < (1/4)  L g Double-Gate (DG) Gate Source Drain Gate T Si T Si < (2/3)  L g 3

Effect of T Si on OFF-state Leakage I OFF = 19  A/  mI OFF = 2.1 nA/  m Leakage Current Density [A/cm 2 V DS = 0.7 V x G G SD G G SD Si Thickness [nm] L g = 25 nm; t ox,eq = 12Å T Si = 10 nmT Si = 20 nm 4

Electrostatics: Under normal operating conditions, the BJT may be viewed electrostatically as two independent pn junctions BJT Types and Definitions The BJT is a 3-terminal device, with two types: PNP and NPN V EB = V E – V B V CB = V C – V B V EC = V E – V C = V EB - V CB V BE = V B – V E V BC = V B – V C V CE = V C – V E = V CB - V EB EE130/230A Fall 2013 Lecture 25, Slide 5 R. F. Pierret, Semiconductor Device Fundamentals, p. 372

BJT Circuit Configurations Output Characteristics for Common-Emitter Configuration EE130/230A Fall 2013 Lecture 25, Slide 6 R. F. Pierret, Semiconductor Device Fundamentals, Fig R. F. Pierret, Semiconductor Device Fundamentals, Fig. 10.3

BJT Modes of Operation Common-emitter output characteristics (I C vs. V CE ) ModeEmitter JunctionCollector Junction CUTOFFreverse bias Forward ACTIVEforward biasreverse bias* Reverse ACTIVEreverse bias*forward bias SATURATIONforward bias *more precisely: not strongly forward biased EE130/230A Fall 2013 Lecture 25, Slide 7 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 10.5

Sample Problem 8

9

Questions regarding the MOSFET design project? 10 Happy Holidays!