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TECHNOLOGY THAT IS DRIVING THE WORLD VLSI AND ASIC DESIGN VERY LARGE SCALE INTEGRATED CIRCUIT AND APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN © R.Lamsal

DEVELOPMENT IN INTEGRATED CIRCUIT TECHNOLOGY SMALL SCALE INTEGRATION SSI < 10 TRANSISTORS 10 TO 100 TRANSISTORS MEDIUM SCALE INTEGRATION MSI LARGE SCALE INTEGRATION LSI 100 TO 1,000 TRANSISTORS VERY LARGE SCALE INTEGRATION VLSI MORE THAN 1000 TO MILLION OF TRANSISTORS ULTRA VLSI © R.Lamsal

VLSI DESIGN CYCLE Design specification HDL CAPTURE RTL SIMULATION NETLIST GENERATION IMPLEMENTATION IN FPGA PLACEMENT,ROUTING POSTLAYOUT SIMULATION,MASKING PACKAGING © R.Lamsal

VLSI DESIGN DOMAINS ALGORITHM PROCESSORS DATA PATH; ALU,REGISTERS Behavioral Structural Physical 1 2 3 ALGORITHM PROCESSORS DATA PATH; ALU,REGISTERS RTL (HDL) LOGIC TRANSISTOR TRANSISTOR CELL. CHIP,MODULE BOARD,SYSTEM © R.Lamsal

HDL incorporates timing feature to represent real hardware. Introduction to HDL Hardware descriptive languages are used purely to describe the digital circuits in various level of abstraction ranging from gate to board and system level. HDL differs from conventional HLL in the sense they make use of concurrency however sequential option is also provided. HDL incorporates timing feature to represent real hardware. © R.Lamsal

AND GATE C<=A AND B after propagation delay; A C Some delay occurs To pass the input Signal at the output A C B C<=A AND B after propagation delay; © R.Lamsal

Transistor representation of And gate Delay occurs due to RC effect of the transistor. VDD C B A Acts as a capacitor © R.Lamsal

Placement TYPE1 Cell A Cell C Cell B Cell D Cell E Cell F © R.Lamsal

PLACEMENT TYPE2 Cell B Cell F Cell A Cell C Cell D Cell E © R.Lamsal

ROUTING Cell A Cell C Cell B Cell D Cell F Cell E © R.Lamsal

Nmos transistor gate source Drain © R.Lamsal

FABRICATION OF NMOS TRANSISTOR BASE SILICON SIO2 ADDED AT THE TOP PHOTOMASKING AND UV RAYS Polysilicon and diffusion To create base source and drain region Metaliziation © R.Lamsal

IMPORTANT PARAMETERS TO BE CONSIDERED WHILE DESIGINING THE CHIP. 1. POWER 2.SPEED 3.AREA © R.Lamsal

EXAMPLE FULL ADDER FULL ADDER A CARRYOUT B SUM CIN © R.Lamsal

TRUTH TABLE A B CIN SUM CARRYOUT Sum<= A XOR B XOR CIN ; 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Sum<= A XOR B XOR CIN ; Carry<= (A AND B) OR ( A AND CIN) OR (B AND CIN) ; © R.Lamsal

VHDL DESCRIPTION library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fulladder1 is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; CARRYout : out std_logic; SUM : out std_logic); end fulladder1; architecture Behavioral of fulladder1 is begin SUM<=a xor b xor cin; CARRYOUT<=(a and b )or (a and cin) or (b and cin); end Behavioral; © R.Lamsal

SIMULATION WAVE © R.Lamsal

LIST TABLE © R.Lamsal

RTL SCHEMETIC © R.Lamsal

SYNTHESIS © R.Lamsal

© R.Lamsal