May 16, 20001

2 USB 2.0 Hub Additions John Garney Hub Working Group Chair Intel Corporation John Garney Hub Working Group Chair Intel Corporation

May 16, Hub Additions w Requirements and Architecture – Additions to USB1.1 w Transaction Translator w Bulk/Control Transaction Handling w Isochronous/Interrupt Transaction Handling w Additions to Chapter 11

May 16, Requirements: w Provide high-speed expansion w Isolate full/low-speed from high-speed – Avoid lower speed impact on HS, i.e., LS impact on FS w All USB2.0 Hub Ports support HS/FS/LS w Optional: standardized port indicators (LEDs)

May 16, System SW Client Driver USB 1.1 Device HS Hub USB 1.1 Hub USB 1.1 Device HS Device USB 2.0 Host Controller Controller Full/Low Speed High Speed Only (2 x 12Mb/s Capacity) Hub In High Speed System w Hub provides high-speed expansion (ala 1.1 hub) w Hub provides additional classic bus(es) – Same total number of devices per USB2.0 Host Controller (e.g. 127) w Greater end user value than classic hub – Performance, expansion and ease of use w Hub is user selected device (not required for all systems)

May 16, Reuse Classic Hub Design Knowledge Reuse Classic Hub Design Knowledge HS/Classic Hub State MachineHS/Classic Machine HS/Classic Hub Repeater Repeater Controller Controller High Speed Only Port Hub “Classic Pieces” w Repeater – High speed signaling u Also, FS/LS signaling for 1.1 compatibility – Reclocking w State Machine – HS termination sequencing u HS Detect, Reset, Suspend, Resume w Hub Controller – Respond to hub device class requests/events

May 16, Hub Architecture w Same as classic hub: – High & full/low-speed repeaters, determined by upstream facing link – Hub controller – No different then classic USB besides high-speed signaling w Minor changes from classic hub: – Hub state machine (HS detect, HS termination transitions, test mode) w New in hub: – Transaction Translator – Routing logic HS/Classic Hub Controller ControllerTransactionTranslatorTransactionTranslator Full/LowSpeed High Speed Only..... HS/Classic Hub State Machine Machine Routing Logic Port HS/Classic Hub Repeater Repeater

May 16, Routing Logic Routing Logic TransactionTranslatorTransactionTranslator Full/LowSpeed High Speed Only Port Repeater, Controller,... Port Hub New Pieces w Port Routing Logic – Controllable electrical connection between: u Full/Low (Transaction Translator), or u High-Speed (Repeater) – Route done once per device reset w Transaction Translator – Major addition for USB 2.0 – Uses split transaction protocol HC support.....

May 16, Host Controller / TT Interactions HostHost DeviceDevice TTTT X X2 TT buffers full/low speed transaction information (X) locally  TT buffers full/low speed transaction information (X) locally 1 – SPLIT-s, OUT, DATAx (Start-split)  Host Controller issues start-split transaction to TT TTTT R R ,ACK TT buffers full/low speed transaction results (R) locally  TT buffers full/low speed transaction results (R) locally 3 - OUT, DATAx,...  TT issues full/low speed transaction on downstream bus 6 - …,ACK 6 - …,ACK  TT responds with results InterruptOutExample 5 – SPLIT-c, OUT, … (Complete-split)  Host Controller issues complete-split transaction to TT

May 16, Transaction Translator Overview w Two separate portions to Transaction Translator – Bulk/Control support – Interrupt/Isochronous support w Bulk/Control uses USB flow control to make progress – PING not used w Interrupt/Isochronous uses a scheduled full/low speed transaction “pipeline” w Separate buffers are used for each TT portion Transaction Translator Bulk & Control Bulk & Control Interrupt & Isochronous Interrupt & Isochronous

May 16, TT Bulk / Control w TT buffers 2 or more bulk/control transactions w TT issues full/low speed transaction when no periodic transactions pending w Host controller issues split transactions to TT – Allows starting/completing full/low-speed transactions each microframe – Normal approach of “bandwidth reclamation” is used – Tries to issue HS start-split; if successful, next attempt does complete-split TTTT Bulk/Ctrl #1 Bulk/Ctrl #2 High Speed Start-/Complete-Split Full/Low Speed Transaction

May 16, TT Int. / Isoch. Pipeline w Host software budgets when full/low-speed transaction will run w Host schedules start-split before “earliest” start time w Host schedules complete-split at “latest” finish times w Scheduling accounts for variation due to bit-stuffing and timeouts, etc. TTTT High Speed Start-Split High Speed Complete-Split Start-splitFIFOStart-splitFIFOComplete-splitFIFOComplete-splitFIFO StartHandlerStartHandlerCompleteHandlerCompleteHandler Full/LowHandlerFull/LowHandler

May 16, TTTT Start-split Start-splitFIFO FIFOComplete-splitFIFOComplete-splitFIFO Full/LowHandlerFull/LowHandler StartHandlerStartHandlerCompleteHandlerCompleteHandler X X2  TT buffers full/low speed transaction information locally 1 – SPLIT-s, OUT, DATAx  Host Controller issues start-split transaction to TT 3 - OUT, DATAx,...  TT issues full/low speed transaction on downstream bus 5 – SPLIT-c, OUT,... 5 – SPLIT-c, OUT,...  Host Controller issues complete-split transaction to TT 6 - …,ACK 6 - …,ACK  TT responds with results Example: Int. OUT Split Trans. R R ,ACK  TT buffers full/low speed transaction results locally Start-split Start-splitFIFO FIFO

May 16, Hub Cost / Complexity Estimate w Classic Hub + new things – Classic Hub - implementation dependent, but knowable baseline – New things u Signaling Ô Required for any High-Speed device u Logic (routing, TT) u RAM (buffer space, transaction pipeline) w Total (approximate) – 40KGates Bytes with 4 downstream ports – 28KGates + (3KG * # of downstream ports) Bytes TT FIFOs TT Logic Port High-Speed “Classic Hub” Port Routing Logic

May 16, USB2.0 Hub Additions Summary w Hub Ports Support all Speeds (High/Full/Low) – Isolation of High and Full/Low Speeds via TT u Simultaneous High and Full/Low-Speed Transactions – Full/Low Speed (12Mb/s) bus per TT u Can be TT per hub or TT per port w TT Internals Overview – Bulk/Control buffering – Interrupt/Isochronous scheduled pipeline