MSP432™ MCUs Training Part 4: Clock System & Memory Welcome to part four of the MSP432 MCU Training series. In this section we will cover the clock system and the memory system. Both are unique and new to the MSP432P4XX Family.

CS | High-level Features Flexible clock sources & distribution: 5 clocks from 7 sources (2 external, 5 internal) Selections suitable for high-speed & low-power operations Wide range of operating frequency 10kHz to 48 MHz Fine intermediate steps with dividers & tuning Configurable & robust system: Run-time lockable configuration Failsafe mechanism with interrupts for external sources From a high level, the clock system on MSP432 is highly flexible with a wide array of clock sources and distributions. You can essentially mix and match clock sources to be used with each peripheral. The clock systems are divided into two domains, one suitable for high speed high performance operations while the second one is more optimized for the ultra-low power consumption. So these two clock groups can be combined to cover a wide range of operating frequency, starting at just 10KHz all the way to 48MHz. There are also many features that are built into the clock system to ensure the robust operations that could be easily be configured on the fly, as well as different fail safe mechanisms that allows you to automatically switch back to internal sources in the event that external sources become unavailable, such as crystal or oscillator fault.

CS | HF & LF Oscillators HF LF ✔ Frequency Oscillators MCLK SMCLK HSMCLK ACLK BCLK Comments HF 1-48 MHz DCO ✔ Internal integrated digitally controlled oscillator. HFXT High frequency crystal. Frequency range is SW configurable. 24MHz MODOSC Internal osc. option for peripherals such as ADC 5MHz SYSOSC Internal, direct clock for ADC failsafe for HFXT LF 32kHz LFXT Low-frequency oscillator 32kHz 128kHz REFO Internal low-frequency oscillator. Failsafe* (32kHz) for LFXT 10kHz VLO Internal ULP LF oscillator Clock selection for WDT There are seven total clocks sources available on the MSP432P4XX family. Starting off with high frequency clock sources we have the digitally controlled oscillator or DCO. It is an internal and most popular clock source that allows you to generate high frequency anywhere from 1 to 48 MHz You can also use a high frequency external crystal to source a high speed frequency clock. Both DCO and High Frequency crystal can operate at 48MHz. Next the MODOSC is an internal oscillator that can operate up to 24MHz. MODOSC is suitable for internal analog operations, just ADC or Flash, so the 24MHz clock source is necessary to run the 1 megasamble ADC. For lower frequency operations of the internal peripherals you could also use the SYSOSC. SYSOSC is an oscillator that runs at 5MHz. Moving on to the low frequency clock sources starting off with the low frequency crystal. It is a typical 32KHz crystal that you can use to run an accurate RTC clock for example. We also have an internal oscillator called REFO. REFO is an internal oscillator that can generate a 128KHz clock signal it can also be divided down to 32KHz.Lasty we have a very low frequency oscillator, it is yet another internal oscillator that can generate a 10KHz clock signal. So altogether we have seven clock sources. And these seven clock sources can be used to feed into five different clock tabs on the MSP432 starting off with MCLK which is the main clock being used to drive CPU as well as possibly DMA operations. Then we have two peripheral clocks, one is SMCLK and the other one is High Speed SMCLK also known as HSMCLK and these two are used to drive different peripherals such as ADC, high speed timers as well as communication modules. There are two additional clock tabs that we could use on MSP43; these are the low frequency clocks ACLK and BCLK. So two particular clocks are particularly used for low frequency and low power modes since they are optimized for ultra-low power mode. So in particular ACLK and BCLK can operate anywhere from 128KHz all the way down to 10KHz. So as you can see we have a pretty flexible array of clock sources as well as clocks that we could use on MSP432. The checkboxes here that you can see are the possible configurations. So for example, you could use DCO to drive MCLK or use MDOSC to drive SMCLK, so on and so forth. One particular clock source that we would like to cover in more details that is unique to MSP432 is the DCO

CS | High-accuracy tune-able DCO 6 tune-able frequency ranges Each range has calibrated center frequency Example: [8-16MHz] range has a calibrated 12MHz center frequency Tune-able within each frequency range Center Frequency +/- 212 steps  DCOTUNE register DCO accuracy: Internal resistor: + 2.65 % [Calibrated] External resistor : + 0.4 % [91kΩ + 0.1% ] Failsafe for internal resistor mode On a typical DCO system the user could select from a number of pre-calibrated frequencies and these pre-calibrated frequencies are usually pretty accurate even across temperature and voltage. However if you need to come up with your own frequency that is not one of the pre-calibrated values , it is also quite difficult to do so in a DCO system with typically requires calibration that needs to be done at production. So the DCO of the MSP432 introduces a new way of doing on the fly calibrations. So first off the DCO still provides six pre=calibrated frequencies starting at 1.5,3,6 all the way to 48MHz. What’s new is about this DCO system is that it allows you to tune to any particular frequency in between these ranges. So starting off with the pre-calibrated frequency for example the 12MHZ, now the range for this DCO range will be starting from 8 all the way to 16MHz and using a DCO tune register and mechanism to tune. You can actually tune to any frequency value between 8MHz and 16Mhz to the accuracy of 2^12 steps. So this unique capability allows you to on the fly retune your DCO to any frequency that your application needs. If you have a particular communication baud rate for UART for example that is not met by any of the existing calibrated frequencies you can use this on the fly tuning capability to determine your exact frequency that you need. Not only providing you with a tuning capability, the DCO on MSP432, also maintains high accuracy across temperature and voltage. Using an internal resister you can achieve 2.65% accuracy. However you do have the option to improve this accuracy all the way down to 0.4% using one external resistor value of 91KOhlms with 0.1 tolerance. With the help of MSP432 driverlib API you can actually just use one API to tune your application to any frequency from 1.5 all the way to 48MHz. Frequency Range 4MHz 8MHz 16MHz 1.5 3MHz 6MHz 12MHz 24MHz 48MHz Calibrated Center Frequency

Memory | Overview Flash SRAM ROM BSL Memory Size Speed Features 256kB + 4kB Sector: 4kB 16MHz Speed boost with 128-bit buffer & pre-fetch Powerful security features SRAM 64kB Bank: 8kB 48MHz Dynamic bank power-down & retention options for low power ROM 32kB Robust DriverLib APIs integrated to save application space Lower power execution BSL 8kB UART/I2C/SPI Boot-Strap Loader provided Moving on to memory. On the first device of the MSP432P series the MSP432P41R, the flash memory comes with 256 Kilobytes with memory. The flash operates at 16MHz it also contains speed boost capabilities with 128bit buffer and pre-fetch mechanisms. The MSP432P41R also comes with 64Kilobytes of SRAM memory. These 64 kilobytes are broken down into 8 banks each with 8 Kb of memory. This allows you to individually control the power to each SRAM bank to optimize the power. The MSP432 also comes with 32Kb of ROM memory, what’s stored into rom is a robust MSP432 DriverLib API that are integrated to save the application space. ROM memory also requires less power to execute from; in addition it also requires a single cycle execution all the way up to 48Mhz, so this is definitely a plus and a benefit when using ROM. The MSP432 is also preprogrammed with a boot strap loader or BSL. The BSL is preprogrammed into the Flash Memory; however you do have the option to program with your own custom BSL. However the factory BSL comes preloaded with all three serial communication flavors provided, including UART, I2C and SPI so you can use this serial communication mechanism to update your firmware in the field, in the event that a JTag access is no longer possible *Possible change: programmable BSL in next devices/revisions

} Memory | Flash 256kB Bank 1 Bank 2 INFO 128kB 4kB Individually [un-]protected from write/erase INFO > 105 erase cycles Independent banks simultaneous read/execute and program/erase operations 128-bit buffer Power savings & higher effective speed with ARM’s pre-fetch Hardware assisted operations Burst data comparison for fixed patterns (data fill check) Flash program modes with auto-computed parity & auto-verify: Write immediate, 128-bit full word write, or 4*128-bit burst mode Flexible Code security & protection options: Individual Flash IP sector protection, further secured/protected with MPU Up to 4 IP-protection memory zones So starting off with Flash, the flash architecture on the MSP432 is that the flash is broken up into two banks. Each bank 128Kb. The flash memory is also broken up into sectors with each sector size being 4Kb, this allows you to individually control, protect or unprotect each sector from any erase or write operation. So this could become quite handy when you form a mass erase on the whole memory and you can still individually protect certain flash sectors. Since the flash memory is broken up into two independent banks, developers can actually leverage this feature to simultaneously read or execute from one bank while performing an erase or possibly program operation from another, this allows the application not to waste any time on flash operation and it can actually execute code in parallel. As we mentioned before, the flash memory executes at the maximum speed of 16MHz, so when the system is running at a higher speed than that, all the way up to 48MHz, a buffer is required in order to improve the effective speed of the flash, so we have implemented a 128-bit buffer that allows the CPU to pre-fetch the memory into the system while running at a higher speed than 16MHz. For various flash programs and erase operations, the flash controller also provides hardware engines that assist with certain operations, such as verification process a little bit easier or to perform a burst mode when it comes to writing to flash. In addition to the flash controller the MSP432 also enables several flexible code security and protection options we will cover this in a later sections. To quickly cover the highlights, you could use the ARM provided memory protection unit to individually secure and protect each flash memory region from execution, from writing or from reading accesses. Software IP vendors can also leverage up to four IP protected memory areas to securely deliver the black box IP solutions to another customer. Again this feature will be discussed in more details in a later section of the training.

Memory | RAM Up to 64KB of banked SRAM architecture 8 dynamically configurable banks: Enable/disable banks to optimize active mode power consumption Retain/not retain content in LPM3 to minimize SRAM leakage power consumption SRAM banks Memory size Bank 0 enable/retention (always enabled) 8KB Bank 1 enable/retention 16KB Bank 2 enable/retention 24KB . . . … Bank 6 enable/retention 56KB Bank 7 enable/retention 64KB On MSP432 there are 63 Kb of RAM memories. And the 64Kb of RAM is broken up into eight dynamically configurable banks, each with 8Kb of memory. For each of the RAM banks there are two options that you can choose in order to optimize the power consumption. First off you can actually enable or disable the banks entirely, and this will shut off any power consumption to the bank. The second option you can also choose to retain or not retain a content in LPM3 to minimize the SRAM leakage in power consumption .In this scenario, all eight SRAM Banks can be active in active mode, however for the SRAM banks that do not retain in memory you can choose to dynamically disregard this content and shut down these banks when the device enters LPM3 mode. This allows for less SRAM leakage power consumption of the device. Ultimately driving the overall device power consumption significantly down.

Memory | Memory Map 256kB + 4kB Interrupt Vector Table Application Code 0x00000000 Flash 0x01000000 ROM 0x20000000 SRAM 0x22000000 Bit-banded SRAM 0x40000000 Peripherals (Registers) 0x42000000 Bit-banded Peripherals 0xE0000000 Instrumentation, ETM, etc. Peripheral Driver Library Bit-Band Ultra-low-leakage SRAM 64kB = 8 x 8kB banks Bit-banded Bit-Band So the MSP432 follows the standardized Cortex-M Memory Map. Starting off with the Flash memory located at the first area in the memory, starting at 0x00. This is where your interrupt vector table as well as your main application code resides. Moving on the ROM memory is located at 0x01000000; this is where the MSP432 peripheral driver library or DriverLib is located. Next you have the SRAM region which is also bit-banded into the bit-band region of SRAM. Next you have the SRAM memory located at 0x2000000, the SRAM memory also being bit-banded allowing you for individual bit access. Moving on you have the peripheral registers located at 0x40000000, the peripheral memory is also being bit-banded allowing you to control each bit of each peripheral register. Last but not least we have the instrumentation as well as the debugging interfaces. These registers are located at the right end of the memory map starting at 0xE0000000. Peripheral Space Register directly accessible Bit-banded

Power, Clock, & Memory | Overall System Design Regulator: DC-DC or LDO DC-DC yields higher efficiency than LDO at higher speed DC-DC requires longer start-up time and transitions from Sleep Modes Flash wait states @ MCLK > 12MHz for VCORE = 0 @ MCLK > 16MHz for VCORE = 1 VCORE level @ MCLK > 24MHz SystemFrequency VCORE LDO/DC-DC* Flash Wait States 0-12MHz LDO 12-16MHz 1 16-24MHz 24-32MHz DC-DC 32-48MHz 2 So tying everything together, in this section we have covered the clock and the memory system and last section we covered the power measurement system of the MSP432 and there are actually quite a few dependencies between the two scenarios. Having a better understanding of how these modules are related to each other will definitely help you build a more robust and more efficient MSP432 application. So first off the number one requirement for any application is the CPU speed, and depending on the CPU speed you must determine the right power measurement configuration as well as the memory measurement configuration that meets that requirement. So for example on MSP432 if the system runs anywhere from 0-24MHz, you can use a VCORE level 0, however if the system runs anywhere from 24 to 48, you would need to boost the VCORE level 1. As mentioned earlier, the flash runs up to 16MHz so if the system runs between 0 and 16, you don’t need a flash boot state. But anywhere from 16-32, you will need to increase the flash boot state to 1 and similarly if the system runs from 32-48 MHz you would need to increase the flash boot state to 2. Last but not least, one thing that could contribute significantly to overall device power consumption is which regulator to use for which frequency. If you could recall from Section 3, when we talked about the power measurement system, there are two regulators provided on the MSP432, the DCDC as well as the LDO and usually the DCDC uses higher efficiency as the LDO in higher speed. So as you increase the system frequency you might want to start thing about investing and start using the DCDC. So with that we have concluded the part 4 of the training series, where we have covered the clock and the memory features of the MSP432. Thanks for watching!