© 2001 By Default! A Free sample background from Slide 1 Gigabit Optical Ethernet ECE 4006C – Spring 2002 – G1 Team Ryan Baldwin David Gewertz Geoffrey Sizemore

© 2001 By Default! A Free sample background from Slide 2 Overview Background on Ethernet Technology Background on Ethernet Technology –from classical Ethernet standards to Gb Installation and testing of legacy Intel/Agilent test-bed Installation and testing of legacy Intel/Agilent test-bed Set-up and testing of Maxim Evaluation Boards Set-up and testing of Maxim Evaluation Boards Design, assembly, and testing of prototype receiver module using Max3266 and Max3264 chips Design, assembly, and testing of prototype receiver module using Max3266 and Max3264 chips

© 2001 By Default! A Free sample background from Slide 3 Ethernet Ethernet invention in Xerox Palo Alto Research Center by Dr Metcalf Ethernet invention in Xerox Palo Alto Research Center by Dr Metcalf –Coincided with the introduction of personal computers Initially 3 Mbps, standardized at 10 Mbps Initially 3 Mbps, standardized at 10 Mbps 1 and 10 Gbps on the horizon 1 and 10 Gbps on the horizon

© 2001 By Default! A Free sample background from Slide 4 Common Considerations Bandwidth Bandwidth –80-20 rule –Ethernet vs. ATM or FDDI Backbone, desktopBackbone, desktop Backwards compatibility Backwards compatibility –OSI stack –Physical layer Connectors and cablingConnectors and cabling

© 2001 By Default! A Free sample background from Slide 5 Implementation Using Fiber Fiber is replacing UTP cable Fiber is replacing UTP cable Why? Why? –Better performance characteristics over longer distances For Gb data rates: UTP < 100 meters Fiber < 260 meters –Higher bandwidth capabilities –Integration with fiber backbone

© 2001 By Default! A Free sample background from Slide 6 Cabling Overview Four mediums: 2 Fiber-based, 2 Copper-based (1000BaseSX, 1000BaseLX, 1000BaseT, 1000BaseCX) Four mediums: 2 Fiber-based, 2 Copper-based (1000BaseSX, 1000BaseLX, 1000BaseT, 1000BaseCX) Fiber allows greater distances, Copper offers greater flexibility Fiber allows greater distances, Copper offers greater flexibility

© 2001 By Default! A Free sample background from Slide 7 Cabling Technologies

© 2001 By Default! A Free sample background from Slide 8 Previous Team’s Progress Design Team Objectives Design Team Objectives –Separation of optical transceiver from Intel card –Redesign and fabrication of new board containing optical functionality –Reintegration of board with Intel setup –Verification to meet optical ethernet specifications –Use of evaluation kits in further design efforts

© 2001 By Default! A Free sample background from Slide 9 Pitfalls and Resolutions

© 2001 By Default! A Free sample background from Slide 10 Final Circuit Diagram (Fall 2001)

© 2001 By Default! A Free sample background from Slide 11 Maxim Evaluation Kits MAX3266 Evaluation Board Diagram MAX3266 Evaluation Board Diagram Photodiode emulation circuit replaced by photodetector

© 2001 By Default! A Free sample background from Slide 12 Maxim Evaluation Kits Circuit Modifications to Minimize Current Loss Circuit Modifications to Minimize Current Loss –Replacing series resistors and adding a 67-Ohm resistor in parallel

© 2001 By Default! A Free sample background from Slide 13 MAX3266 Board Functionality Photodiode emulation Photodiode emulation –inexpensively mimic the output of a photodetector for chip feature testing Transimpedance Amplifier (TIA) on chip Transimpedance Amplifier (TIA) on chip –converts current to voltage –converts single-ended input to differential output –1 mA p-p input = 250 mV p-p output –10 micro-A p-p input = 2.5 mV p-p output

© 2001 By Default! A Free sample background from Slide 14 Maxim Evaluation Kits MAX3264 Evaluation Board Diagram MAX3264 Evaluation Board Diagram

© 2001 By Default! A Free sample background from Slide 15 MAX3264 Board Functionality Proper termination impedance and series capacitors to maintain voltage regularity Proper termination impedance and series capacitors to maintain voltage regularity Buffer on chip Buffer on chip –maintains integrity of output from TIA Limiting Amplifier on chip Limiting Amplifier on chip –provides 55 dB gain with 1.2 Volt max –low jitter enables higher speeds RMS Power Detection RMS Power Detection

© 2001 By Default! A Free sample background from Slide 16 Testing and Verification Pattern Generator Pattern Generator –Tektronix GTS 1250 (1250 Mb/s) –desired BER = or 1 error every terabit Example - For a 4 MB MP3, that would be one bit error for every 31,000 songs transferredExample - For a 4 MB MP3, that would be one bit error for every 31,000 songs transferred Tektronix CSA 7xxx Scope Tektronix CSA 7xxx Scope –accurately measures and records Gb eye diagrams –uses specially designed Communications Signal Analyzer software

© 2001 By Default! A Free sample background from Slide 17 Initial Design Idea Single PCB with both chips Single PCB with both chips Interface with other design groups (OE, TX) Interface with other design groups (OE, TX) Interference-free implementation of a single power source to drive all active components Interference-free implementation of a single power source to drive all active components

© 2001 By Default! A Free sample background from Slide 18 Intel Gb Test-bed

© 2001 By Default! A Free sample background from Slide 19 Intel Gb Test-bed Results Testing showed no packet loss *discrepancy in tx/rx packets due to lack of termination synchronization between transmitter and receiver

© 2001 By Default! A Free sample background from Slide 20 Block Diagram of Maxim Setup Oscilloscope TDS GND Dual Output Variable Power Supply BERTS GTS1250 Out +Out - Note: Scope gets clock signal from BERTS

© 2001 By Default! A Free sample background from Slide 21 Simulated Maxim Setup PRBS Signal (2 7 -1)TDS7154 Screen Capture Maxim Boards

© 2001 By Default! A Free sample background from Slide 22 Maxim Knowledge Lack of DC cancellation network created huge jitter Single Power supply implementation did not introduce noise to system due to filtering networks on the evaluation boards

© 2001 By Default! A Free sample background from Slide 23 Unused Maxim Features

© 2001 By Default! A Free sample background from Slide 24 Initial Draft of Layout

© 2001 By Default! A Free sample background from Slide 25 PCB Layout Software Extensive library of components and easy-to-use interface And it’s “FREE! FREE! FREE!” © Matthew Lesko FREE!

© 2001 By Default! A Free sample background from Slide 26 Receiver Board Layout SMA Connectors Power Connectors Note: Backwards! Supply Traces GND Traces Note: SMA connectors connected to bottom of board

© 2001 By Default! A Free sample background from Slide 27 Prototype Board with Results K28.5 Input PRBS7 Input K28.5 Bit Pattern

© 2001 By Default! A Free sample background from Slide 28 Problems Encountered Oscillation in bit pattern results with variation in power jack setup. Cross-talk seen when power wires were in close proximity to board, SMA cables, or each other. Possible ground interference issues could have affected results. Here

© 2001 By Default! A Free sample background from Slide 29 Conclusions Investigated Background on Ethernet Technology Investigated Background on Ethernet Technology Installed and tested legacy Intel/Agilent test- bed from Fall 2001 Installed and tested legacy Intel/Agilent test- bed from Fall 2001 Set-up and tested Maxim Evaluation Boards Set-up and tested Maxim Evaluation Boards Designed, assembled, and tested prototype receiver module using Max3266 and Max3264 chips Designed, assembled, and tested prototype receiver module using Max3266 and Max3264 chips Next group should examine oscillation and noise inconsistencies Next group should examine oscillation and noise inconsistencies