Advisor: Dr. Chandra Christopher Picard Michael Neuberg

 Radar Basics  CSU Facilities  Hardware Accelerator  Pawnee Update  Next Semester Plans

 Radar- RAdio Detection And Ranging  Transmits microwaves  Elevation position, ∅  Azimuth Position, Ѳ National Weather Service

Old CHILL Dish and Antenna Constructing new dish location Generates waveform of signals Builds up signal and transmits

Pawnee Facility Inside the Radome GPS, DSP, etc Signal Monitors and Generator

 Parametric Time Domain Method (PTDM)  Prevents the need for Fourier Transforms  Prevents signal Leakage  Problem  Requires calculating inverses and determinates of large matrices  Can not perform calculations in real time on standard CPU  Solution Requirements  Implement PTDM algorithm in real time

 Graphics Card  Can perform multiple operations in parallel  Designed to optimize required matrix calculations  Nvidia CUDA  Compute Unified Device Architecture

Specification Multiprocessor16 Memory1.5 GB Shared Memory16 KB per MP Registers8192 per MP Threads768 Memory Bandwidth 76.8 GB/Sec Hewlett Packard xw 9400 workstation

 Replace synchros with optical encoders  Interface encoders and signal processor with FPGA  Design and build interface board  Improves radar tracking and positioning

 Why replace synchros?  Stegmann ARS-20 absolute encoder  Rotating encoder disk  Enhanced resolution  Reduces noise and cost with less wires

 Xilinx Spartan-3E FPGA  BASYS board  Printed Circuit Board  VHDL programming  Generate clock signal

 Donations  CHILL Radar Facility  Encoders, development board, circuit board ($1,250)  Hewlett Packard  xw 9400 workstation, 2 Quadro Fx 5600 ($4,500)

Hardware Accelerator TasksStart DateFinish Date Durations Get system setup and successfully run simple test CUDA programs. 12/10/071/21/086 Weeks Finish CUDA code that optimizes performance on real sample data 1/21/082/18/084 Weeks Integrate CUDA code with algorithm code. 2/18/083/31/086 Weeks Configure system to interact with radar interface and integrate system into site. 3/31/084/14/082 Weeks Hardware Update TasksStart DateFinish Date Durations Finish programming interface for FPGA (Combine data, state machine, transmit) /27/0812 Weeks Design printed circuit board1/27/083/23/088 Weeks Build, test, and debug circuit board3/23/084/13/083 Weeks

 design/AY07/radar/index.html  Acknowledgments  Dr. Chandra  Jim George  Cuong Nguyen  Darryl Benally  Hewlett Packard