PEALL: Power Efficient And Low Latency A 40 MSPS 12 bits SAR ADC for LTD Joel Bouvier, Daniel Dzahini, Carolina Gabaldon, Laurent Gallin-Martel Fatah Ellah Rarbi, Benjamin Trocme, Mohamed Zeloufi LPSC, Universite Grenoble-Alpes, CNRS/IN2P3 LPSC Grenoble1

Outline Background in ADC design at LPSC – From Pipeline to SAR ADC Architecture of asynchronous SAR ADC Measurements – Proto 1 with external reference voltage – Proto2 with embedded reference Problems identified & solutions Schedule up to production Conclusion LPSC Grenoble 2

ADC & DAC design are a long term research in our lab since 1999 A full behavioral study was made on pipeline ADC – Each parasitic effect analyzed. (Rarbi’s thesis) 12 bits, 25 MSPS pipeline 14 bits, 15 MSPS DAC Many prototypes published in CMOS.35µm Strong background in converters design 3 A dB 1.5 bit stage Digital correction 2.5 bit stage 3 bit flash Bias stage LPSC Grenoble

First analog memory chip with embedded ADC in Collaboration with CEA Saclay. CMOS 0,35µm: 3x7mm ADC IP for NECTAR Chip: CTA experiment INL DNL LPSC Grenoble4

Why moving from pipeline to SAR? PIPELINE Architecture Allow high speed design Natural important latency Power dissipation (amplifier) ∆V ref means more INL Mismatch in capacitors (*) V ref buffer bandwidth (*) Clock frequency (as sampling) Sampling time (large: 12.5ns) Total die area could be large Scaling to future 65nm process SAR Architecture IBM 130 allows high speed The best latency (after a Flash) The best power dissipation ∆V ref does not means INL Mismatch in capacitors (**) V ref buffer bandwidth (**) Higher frequency clock (**) Sampling time brief  3 or 4ns Die area very small Ready for scaling to 65nm LPSC Grenoble5

Challenges & solutions for the SAR Difficulties  Our solutions Capacitors Mismatch V ref buffer bandwidth Higher frequency clock Short sampling time  A trimming optimization  A huge task! We did it  Asynchronous design (only 40 MHz )  A segmented scheme  Bootstrap switches LPSC Grenoble6

Power Efficient and Low Latency SAR ADC Main features of our PEALL ADC: – Asynchronous high speed clock (640 MHz) internally generated from the 40 MHz clock and the output of the comparators. – Fully differential configuration: array of capacitors is segmented in 2  Small area – Trimming feature to compensate from the capacitor mismatch 16 capacitors in parallel that can be disabled on demand to achieve the optimal value for the termination capacitor. Value can be tuned by slow control – Very basic and small digital part  less affected by SEE that is the main radiation concern in HL-LHC PEALL ADC architecture (1) LPSC Grenoble7

PEALL ADC architecture (2) trimming ± Vref SARSAR Fast Clk Bloc 40Mhz LVDS Output serialiser registers 640Mhz 640MHz Readout The unit capacitor is 100 fF leading to a total equivalent of 3,2pF at each input The ADC is synchronized with the output stage serialiser. LPSC Grenoble8

READ-OUT Interface Timing diagram: SMPL, SAR clock, End Conversion are generated internally. Read clock comes from outside to synchronize the serialiser. LPSC Grenoble9 Generated Locally from The master 40MHz

Prototyping & Results All the following measurements were done while all the ADC channels were working in parallel LPSC Grenoble10

2 channel version with external V ref tested in May 2013 – Local clock generator was working properly – The design suffers from sampling noise at the V ref due to inductance problems caused by the bonding wires from the chip to the package A Chip on board made to reduce the inductances from 5nH to 3nH, but we were still limited at 20MSP and ±4LSB of INL 1 st SAR Prototype Packaged prototype Daughter board Chip on board LPSC Grenoble11

1 st Prototype: External V ref limitations For L=5nH; σ=10.24mV For L=3nH; σ=9.5mV Measured noise on both V ref nodes: Packaged prototype Chip on board VrefN=0.25V VrefP=1.25V V ref never settles properly 20 ns LPSC Grenoble12

V ref settling and noise problems & solutions Simulations for 1 st prototype: External V ref Simulation for 2 nd prototype: Embedded V ref 300mV 100mV LPSC Grenoble13

2 nd prototype with 4 channels and embedded V ref – Chip size: 2.8 x 3.4 mm 2 in a QFN 64 package. – Power consumption: 5 mW/ch for core ADC, 27mW/ch with V ref driver and output LVDS (specs: 145mW/ch) Could ease cooling plate design (challenging in LTDB board) – Latency: 25 ns + 9 ns (serialiser) (specs : 200 ns) Could give more time to BackEnd/L1Calo for refined variable computation 2 nd SAR Prototype LPSC Grenoble14

Very challenging integrated V ref The integrated V ref define the dynamic range for the ADC. It is built from a bandgap cell (CERN IP) followed by a very high speed (5 GHz) and low impedance amplifier designed at LPSC. – This amplifier must charge all the capacitors in less than 1 ns. High speed buffer SAR ADC Our testing results confirms that we succeed with the bandwidth of this buffer. – ADC works positively at 40MSPS, with the 640 MHz clock generated. Bandgap was qualify to TID by CERN team (30 mV drift over 200 MRad) Bandgap PTAT IP from CERN 3,2pF ~ mA/1nS LPSC Grenoble15

V ref testing results & improvements A reference voltage 15% lower is found. – Consistency between chips, but the mean value is less than the expected nominal value. The cause of the dispersion was identified as a current mirror mismatch in the amplifier. Solution for next prototype found by MC Simulations. present prototype next prototype LPSC Grenoble16

ADC output noise distribution As expected, the trimming feature has not impact on the random noise (1-2 LSB). Spikes appear at regular codes  reduced but not significantly by the trimming LPSC Grenoble17

Integral Non Linearity Trimming feature is working  INL is progressively reduced Spikes appear at exactly same codes following the noise results INL = ±5 LSB for trimming 16 LPSC Grenoble18

Spikes identified at very specific codes Spikes observed for specific input signal always a fraction of V ref. – It is not a random distribution. – Obvious correlation between “noise” spikes and INL’s spikes. 19 Time 4 8 V input = V V input = VV input = V LPSC Grenoble

INL could be improved by a better segmentation of the capacitor array. 3 emulated configurations: – Improvement in linearity with 7MSB + 5LSB conf. – Total capacitance will not change. Segmentation impact on INL 1 LSB of Linearity is saved by segmentation improvement 2 nd prototype: 5MSB + 7LSB => INL = ±3 6MSB + 6LSB =>INL = ±2.5 7MSB + 5LSB=> INL < ±2 c(LSB) & c(MSB) LPSC Grenoble20

Source & solution for spikes problem Source of the spikes problem: – Segmentation gives a 2 nd order settling time for the DAC. – Meta-stability of the comparator. Spikes could be reduced by a better amplification before the latch comparator. 2 nd prototype: Amp. x1 => INL = ±2 LSB Amp. x4 => INL = ±1 LSB Amp. x8 => INL = ±0.5 LSB LPSC Grenoble21

Dynamic specifications Dynamic performance of the ADC are determined from the FFT for an incoming sinus signal: 100 KHz, 1 MHz and 5 MHz. 5 MHz 100 kHz 1 MHz These results integrate all the limitations: reduce dynamic range spikes jitter (next slides) Chip 8, channel 0, trimming 16 LPSC Grenoble22

ENOB vs. trimming 100 kHz 1 MHz 5 MHz Evolution of all channels vs. trimming capacitor: – ENOB increased when the trimming increased – Most efficient  trimming 16 Chip 8, channel 0 For 5 MHz input signal  ENOB ~ 7.7 – 8.3 LPSC Grenoble23

ENOB stability over this prototyping run ENOB is measured for all channels and for the 11 packaged chips. – Measurement consistent over chips and over channels. – But lower than specifications ~11. LPSC Grenoble24

Lower ENOB - source & solutions Theoretical limitations as a function of jitter Source of ENOB reduction  sampling clock jitter – 1 to10 ps jitter is needed to reach expectations. – Simulation studies of 2 nd prototype: RMS jitter 30 ps or ±100 ps peak to peak Present problem for jitter New jitter simulated Solution: Modifying the architecture of the sampling pulse generator inside the chip. 30 ps LPSC Grenoble25

Crosstalk measurement LPSC Grenoble26 To determine the crosstalk between the ADC channels, a 1 and 5 MHz full scale sine- wave was applied to channel 1 while all the others (0, 2 and 3) are grounded. F in CH1 1 – 01 – 21 – 3 Crosstalk (dB) 1 MHz MHz

Prospects for 3 rd prototype LPSC Grenoble27 Submission of the 3 rd prototype by August Digital part remains unchanged. Minor modifications: – Optimization of the reference voltage. – DAC array segmentation from 5-7 to 7-5 configuration. – Optimization of the sampling clock to improve jitter. – Increase the gain of the first stage of the comparator. Simulations is finished and layout is going on. Starting the test by December 2014.

INL: Improvement expected (Cadence new configuration for SC ADC simulations) LPSC Grenoble28

Radiation of the 2 nd prototype 2 analog boards with 2chips to be irradiated Digital Zedboard For data readout and Ethernet DAQ & control LPSC Grenoble29 Chips SEU irradiation was foreseen last week at Louvain Cyclotron facility, but they cancelled this run at the last moment. Protons of energy greater than 20 MeV with typical cumulated doses of 1- 2*10 13 protons/cm2.

Cost & Resources We have a very small area chip < 8.5mm 2 – Cost estimate for <10mm 2 is less than 300KEu – Packaging: 10KEu Resources: – We were always on time with our schedule (design submission & test). – LPSC has a long passed experience in testing many circuits for ATLAS/LARG (SCA, shaper, smux...) with a home made robot. – We plan 3 possibilities for testing PEALL production: 1.Using our home made robot with our testing hardware & software 2.Submission to a private company with a handling system 3.Using MOSIS testing facilities – With 2mn/chip=> 2.5months for production testing. LPSC Grenoble30

31 Handling system for ASIC test in IN2P3 ATLAS FEB Socket compatible with QFN and easy to open/close LPSC Grenoble

Schedule August 2014: Submission of the upgraded version of PEALL. December 2014-Feb 15: Testing this upgraded version March 2015: (Engineering run for about 500 chips) August to September 2015: test of engineering run. December 2015: Production Run March to September 2016 : Production Test October 2016: Delivery of qualified chips LPSC Grenoble32

Plans for phase II While moving from pipeline to SAR architecture, we made a good choice compatible with 65nm. All the limitations of a SAR ADC are fully understood now. In August 2014, we will submit in the IBM 130nm, our first 12 bits SAR ADC with a redundancy architecture. – A digital correction algorithm is already developed and ready to be evaluated. In 2015, we will move this design in 65nm for a 12 bits and next 14bits with a gain selector stage. We do have an exiting perspective, and all the main critical points of our design are carefully under control. LPSC Grenoble33

Robustness for redundancy SAR + LMS algorithm Present version of binary SAR Redundancy version SAR + correction LPSC Grenoble34

Conclusions 1.SAR architecture was a challenging but good choice, fully compatible with easy scaling to 65nm 2.We positively reach the 40MSPS with V ref fully embedded. 3.This asynchronous 12 bits 40MSPS is a record 4.The latency time, power & chip area are optimal. 5.Minor problems identified and solutions found. 6.Our next prototype will be at the requirement level. 7.Plans for phase 2 with a redundancy version and LMS digital correction. LPSC Grenoble35

BACKUP SLIDES LPSC Grenoble36

Requirements targeted for the ADC Sampling rate40MSPS Dynamic range12 bits Resolution (ENOB)≥11 bits Differential Nonlinearity1 LSB Integral Nonlinearity1LSB Latency200nS Power dissipation145mW LPSC Grenoble37

SAR ADC with sampling capacitors Binary Weighted Capacitor Segmented Binary Weighted Capacitors Thermometer control Capacitors LPSC Grenoble38

R=39 Ohm et sans capa d'entree step 1mV Less nb. of spikes but HIGHER 1st Prototype: COB LPSC Grenoble39

V ref Noise effect (in our Model) SFDR(Vref noise) SNR(Vref noise) THD(Vref noise) LPSC Grenoble40

TID Chip 5 0 to 200Mrad full sweep LPSC Grenoble41 Band gap IP testing results provided by CERN

Robot developed in LPSC for ATLAS (since 1999) One possibility for our production testing LPSC Grenoble42

Irradiations Setup LPSC Grenoble 43 SEE tests: Louvain Cyclotron (proton beam) is our main option at the moment. TID: BNL set-up

Production testing procedure Our present testing system is already split in two parts (Analog board +digital board). This configuration will be used for prod. Testing and only the analog board will be upgraded with a new socket (with easier open & close) Parameters to check: Power consumption; dynamic range; ENOB for trimming 1 and trimming 16 while 5Mhz incoming sinus signal, INL & DNL. LPSC Grenoble44

PhD thesis is going on for phase II SAR ADC 12 to 14 bits A Sub radix configuration has been fully simulated. A binary scheme with redundancy is also studied. An algorithm is written for digital correction purpose. The total power dissipation for the 14 bits in 65nm will be really less than for 12 bits in 130nm !! LPSC Grenoble45

DAC (5MSB + 7LSB)DAC (6MSB + 6LSB)DAC (7MSB + 5LSB) ENOB8,5479,37310,1 SNR53,7858,5363,31 SINAD53,2158,1962,54 THD-62,28-69,36-70,42 Model’s Dynamic parameters for 10% mismatch on segmented capacitor LPSC Grenoble46