May 17, USB 2.0 Transceiver Macrocell Steve McGowan - Intel Corporation Clarence Lewis - Texas Instruments Steve McGowan - Intel Corporation Clarence Lewis - Texas Instruments

May 17, Macrocell Requirements w Simplify the design process for peripheral vendors – Consolidate high speed logic in to a discrete module – Provide a “standard” USB 2.0 hardware interface w Minimize time to market – Decouple ASIC and Peripheral development cycles u Enable standard library elements from ASIC vendors – Peripheral vendors can focus on product specific development u Reuse of existing USB 1.1 SIE logic Overview Enable High Volume Devices

May 17, Overview USB Device Development w Assumptions – Prototyping u FPGA u UTMI Compliant Discrete Transceiver – Production u Low Volume Ô Gate Array Ô UTMI Compliant Discrete Transceiver u High Volume Ô ASIC Ô UTMI Compliant Transceiver Macrocell

May 17, Device Anatomy w USB Transceiver Macrocell (UTM) w Serial Interface Engine w Device Specific Logic Overview ASICASIC Serial Interface Engine Device Specific Logic Endpoint Logic …… SIE Control Logic SIE Control Logic USB 2.0 Endpoint Logic Device Hardware USB 2.0 Transceiver UTM Interface

May 17, Serial Interface Engine w SIE Control Logic – USB Transaction State Machine – PID, Address, and EP match logic – Checks receive completion status – Chains packets into transactions w Endpoint Logic – FIFOs and FIFO control Serial Interface Engine Endpoint Logic … SIE Control Logic Endpoint Logic Control Data In Data Out To Device Specific Logic To Transceiver Overview

May 17, Transceiver Macrocell w Converts USB signaling into a simple interface – USB 2.0 compliant serial interface – Multiple Parallel Data Interface Options – Multiple Speed Options u HS/FS, FS Only, LS Only USB 2.0 USB 2.0 Transceiver Control Data In Data Out To SIE To Bus Overview

May 17, Macrocell Functions w HS and FS signaling and termination w HS receiver squelch w USB clock recovery w Bit stuffing w NRZI encoding w Serializing and deserializing w Data-rate tolerance w Data buffering w Single interface for HS/FS, FS or LS operation Overview

May 17, Block Diagram Control D- D+ DLLDLL FS Interface HS Interface Shared Logic ParallelInterfaceParallelInterface DLLDLL mux BitUnstufferBitUnstufferDeseralizerDeseralizer RX Holding Reg BitStufferBitStufferSeralizerSeralizer TX Holding Reg Reg To SIE Data To USB

May 17, Bit Uni-Directional Interface Options DataIn(0-7)TXValidResetSusepsndMXcvrSelectTermSelectOpMode(0-1)DataOut(0-7)TXReadyRXActiveRXValidCLKRXErrorDPDMLineState(0-1) 8-Bit Interface

May 17, Bit Uni-Directional Interface Options DataIn(8-15) DataIn(0-7) TXValid TXValidH DataBus16_8 Reset SusepsndM XcvrSelect TermSelect OpMode(0-1)DataOut(8-15)DataOut(0-7)TXReadyRXActiveRXValidRXValidHCLKRXErrorDPDMLineState(0-1) 16-Bit Interface

May 17, Bit Bi-Directional Interface Options DataBus16_8DataOut(8-15)DataOut(0-7)TXValidRXValidHData(8-15)Data(0-7)ValidHDataIn(8-15)DataIn(0-7)TXReadyTXValidH 16-Bit Bi-Directional Interface

May 17, How Does the Macrocell Do It? Macrocell Functions

May 17, Macrocell Functions Interface w Packet Engine – Automatically handles SYNC Pattern and EOP w Flow Control – Compensates for Bit Stuffing and Data Rate Tolerance w Primitives for Full Protocol Support w Speed Switching w Clock Generation w Power Control

May 17, Receive w RXActive - Frames Packet w RXValid - Provides Flow Control Macrocell Functions CLK CLK RXActiveRXActive RXValidRXValid DataOut(7:0)DataOut(7:0) PIDPIDDataDataDataData DP/DMDP/DMSYNCSYNCPIDPIDDataDataDataDataEOPEOP

May 17, Transmit w TXValid - Frames Packet w TXReady - Provides Flow Control TXValid DP/DM PID Data SYNC Data CRC EOP TXReady CLK DataIn(7:0) PID Data CRC Data Macrocell Functions

May 17, Macrocell Functions Signals w Flow Control – Receive with data underruns due to removing stuffed bits from the data stream

May 17, Protocol Primitive Support w Resume Assertion w Resume Detection w Suspend Detection w Reset Detection w HS Detection Handshake Macrocell Functions

May 17, Macrocell Functions Operational Modes w Normal Operation – Standard encoding and decoding of serial stream w Non-Driving – Tri-states all transmitters and termination on the bus w Unencoded Data (needed for test modes) – Disable Bit Stuffing and NRZI encoding – Allows transmission and reception of unencoded data

May 17, Resume Assertion w Place Macrocell in “Disable Bit Stuffing and NRZI encoding” mode w Transmit ‘0’ data for K’s (‘1’ data for J’s) w Wait for SE0 SuspendM XcvrSelect & TermSelect 'K' State FS Idle ('J') DP/DM SE0 FS Mode HS Mode TXValid OpMode Mode 2 Mode 0 Macrocell Functions

May 17, Resume Detection w Listen to LineState w Use J to K transition to disable SuspendM w Enter HS mode after K to SE0 transition – Assert XcvrSelect and TermSelect FS Mode HS Mode SuspendM XcvrSelect 'K' State 'J’ State (FS Idle) LineState SE0 OpMode Mode 0 XcvrSelect Macrocell Functions

May 17, Suspend Detection w Watch LineState for 3ms of inactivity (SE0) w Switch to FS mode – Assert XcvrSelect and TermSelect w If J asserted, then enter Suspend State – Assert SuspendM Term Select Last Activity 'J' State SE0 SuspendM LineState Xcvr Select Transceiver suspended Macrocell Functions

May 17, Reset Detection w SE0 is the Idle state in HS mode w After 3ms of inactivity (SE0) switch to FS mode – Assert XcvrSelect and TermSelect w If SE0 asserted then enter Reset – Initiate HS Handshake Detection Term Select Last Activity ’SE0' State SE0 DP/DM Xcvr Select HS Handshake Detection Process HS Handshake Detection Process Macrocell Functions

May 17, HS Detection Handshake w Turn on HS Transceivers with FS Terminations w Drive a “Chirp K” w Detect Chirp K/J Sequence from the Hub w Assert HS Terminations Hub Chirp Sequence Device Chirp Device Chirp TXValid TermSelect XcvrSelect HS Mode Chirp K DP/DM K K J J K K J J K K J J K K J J SE0 SOF HS Detection Handshake Process Macrocell Functions

May 17, Clock Generation w Macrocell supplies clocks to the SIE w Frequency depends on implementation – HS/FS u 60 MHz 8-bit uni-directional u 30 MHz 16-bit uni- or bi-directional – FS Only u 48 MHz 8-bit uni-directional – LS Only u 6 MHz 8-bit uni-directional Macrocell Functions

May 17, Power Control w SuspendM signal – Shuts down clocks – Maintains terminations w Vendor determined Drive Current Control – Enabled during transmits – Enabled by receives – Always on DP DM HS_Current_Source_Enable HS_Drive_Enable HS_Data_Driver_Input High-speed Current Driver Macrocell Functions

May 17, Next Steps w Get the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification – – 1.0 Release Available – No Royalty w Develop to the UTMI Specification w Get your ASIC vendors to provide a UTMI Compliant Macrocells