Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 1 ECE 747 Digital Signal Processing Architecture SoC Lecture – Working with DRAM April 3, 2007 W. Rhett Davis NC State University

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 2 Today’s Lecture l DRAM Introduction l DRAM Latencies

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 3 Introduction l Perhaps more than any other single factor, DRAM heavily influences SoC Architecture l Our goal is to accurately predict the average throughput of our architecture. l Questions we need to answer: For a given architecture, how do we » choose the right data-width for the DRAM? » choose the right clock-frequency for the DRAM? » configure the Dynamic Memory Controller for the correct latencies?

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 4 Types of DRAM l SDRAM (Synchronous DRAM) – Synchronized to bus clock frequency, Achieves higher clock-frequencies than normal DRAM because it is designed to work at a specific frequency l DDR SDRAM (Double Data Rate SDRAM) – Achieves higher throughput by reading/writing data on both clock transitions (rising and falling) » Why is this necessary? Can’t we just use more chips? l DDR2 SDRAM – Allows bus clock to be 2X internal clock of DRAM, achieves higher clock-frequencies l Each of these improvements comes with added latency Because adding a pin to the SoC is one of the most costly design decisions, consumes lots of area and adds lots of wire delay

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 5 Array-Structured Memory Architecture Amplify swing to rail-to-rail amplitude Selects appropriate word Source: Rabaey, et al, Digital Integrated Circuits

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 6 Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Source: Rabaey, et al, Digital Integrated Circuits Most DRAMs are organized in multiple “blocks” or “banks”

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 7 SDRAM Pins l Address pins are in two groups » Column/Row Address pins (each address provided on a different cycle) » Bank Address l Example: 256Mb (32Mx16 – 4banks) » 13 column/row address pins (green) » 2 bank address pins (white) » 16 data pins (blue) Source: Micron 256Mb DDR2 SDRAM Datasheet

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 8 Today’s Lecture l DRAM Introduction l DRAM Latencies

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 9 Types of Latencies l Read/Write Latencies: » CAS/CL » DQSS l Command Latencies » RCD » RP » RAS » RC » RRD » WTR » WR

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 10 CAS Latency (CAS/CL) l “Colmn Address Strobe/Select” Latency – Delay between read command and arrival of data l Source: Micron 256Mb SDRAM Datasheet CAS = 3

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 11 Moving Between Columns/Banks l Reads within the same column and between banks incur no additional latency l Configured for bursts of 4, reads to separate column addresses in different banks Source: Micron 256Mb SDRAM Datasheet

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 12 Data Strobe Delay (DQSS) l Time between issuing of write command and when first data-value is expected to be valid Source: Micron 256Mb DDR2 SDRAM Datasheet

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 13 Command Latencies l The previous latencies don’t affect throughput, because they can be pipelined l Command latencies, however, affect throughput, because they affect how long you must wait before issuing a new command l Commands: » ACTIVE – Activate (or “open”) a row for read/write » PRECHARGE – Precharge (or “close” a row) » READ » WRITE l Only ONE ROW AT A TIME may be active in each bank l A Row must be closed before another one can be opened

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 14 Types of Latencies l Read/Write Latencies: » CAS/CL – Column Address Strobe/Select Latency » DQSS – Data Strobe Delay l Command Latencies » RCD – Row-to-Column or Row Command Delay (ACTIVE to READ or WRITE) » RP – Row Precharge (PRECHARGE to ACTIVE) » RAS – Row Address Strobe/Select (ACTIVE to PRECHARGE) » RC – (ACTIVE to ACTIVE – same bank) » RRD – Row to Row Delay (ACTIVE to ACTIVE – different banks) » WTR – Write to Read Delay (WRITE to READ) » WR – Write Recovery (WRITE to PRECHARGE)

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 15 Command Latencies Illustrated l This figure illustrates which latency value to expect when one command follows another

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 16 RCD, RP, RAS, RC Latencies Source: Micron 256Mb SDRAM Datasheet

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 17 Comparison of Micron Memories 256 Mb SDRAM 256 Mb DDR SDRAM 256 Mb DDR2 SDRAM fclk (MHz) CAS/CL (cyc.)335 RCD (ns)15 RP (ns)15 RAS (ns)3740 RC (ns)6055 RRD (ns) WTR (cyc.)127.5 WR (ns)1415

Spring 2007W. Rhett DavisNC State UniversityECE 747Slide 18 Comparison of Micron Memories 256 Mb SDRAM 256 Mb DDR SDRAM 256 Mb DDR2 SDRAM fclk (MHz) CAS/CL (cyc.)335 RCD (cyc.)335 RP (cyc.)335 RAS (cyc.)7814 RC (cyc.)11 19 RRD (cyc.)323 WTR (cyc.)123 WR (cyc.)335