Chihou Lee, Terry Yao, Alain Mangan, Kenneth Yau, Miles Copeland*, Sorin Voinigescu University of Toronto - Edward S. Rogers, Sr. Dept. of Electrical & Computer Engineering * Professor Emeritus, Carleton University, Ottawa, ON, Canada. SiGe BiCMOS 65-GHz BPSK Transmitter and 30 to 122 GHz LC-Varactor VCOs with up to 21% Tuning Range

Outline Motivation VCO and BPSK transmitter circuit topologies Design methodology for lowest phase noise VCOs Experimental results Conclusions

Motivation Advanced communications (60-GHz radio) and radar systems (77-GHz cruise control). Investigate a systematic VCO design methodology focused on lowest phase noise.

Outline Motivation  VCO and BPSK transmitter circuit topologies Design methodology for lowest phase noise VCOs Experimental results Conclusions

Differential Colpitts Configuration C 2 implemented as accumulation-mode nMOS varactor. Cascode for improved isolation of output from resonant tank, and power gain. L EE & Resistive tail bias with low-pass filter to reduce bias circuit’s noise contribution. Fundamental Mode VCO Topology

Push-Push VCO Topology Active and passive components operate at ½ output frequency Similar topology as fundamental- mode VCO except output is taken at Q 2 & Q 4 ’s base. Intrinsically isolated output. Allows differential tuning (V TUNE+POS, V TUNE,-NEG ).

35-GHz VCO (Fund.)70-GHz VCO (Push-Push) VCO Schematics

BPSK Transmitter Schematic

Outline Motivation VCO and BPSK transmitter circuit topologies  Design methodology for lowest phase noise VCOs Experimental results Conclusions

VCO Design Parameters: V TANK – tank voltage swing Q TANK – tank quality factor J BIAS – current density C 1 :C 2 – capacitance ratio L B – base inductance I BIAS – bias current Designing for Lowest Phase Noise Simulation Test Circuit

1. Optimum C 1 :C 2 Ratio

2. Optimum Current Density (J BIAS ) OPTIMUM J BIAS = optimum noise current density (J opt ) of cascode. OPTIMUM J BIAS

3. Optimum Bias Current (I BIAS )

3. Optimum Base Inductance (L B ) Smallest L B results in Lowest Phase Noise

VCO Design Methodology 1.Maximize quality factor (Q) of resonant tank. 2.Bias transistors at optimum noise current density J opt. Show a simulated plot of 40 GHz & fT, fMAX for cascoded transistor configuration

VCO Design Methodology (con’t) 4.Choose smallest reproducible base inductance (L B ). 5.Sweep I BIAS to minimize phase noise while choosing C 1 :C 2 ratio to maximize V TANK while maintaining f osc. 6.Add inductive emitter degeneration L E. [Li and Rein, JSSC 2003]

VCO Design Space Examined 13 VCOs & Oscillators fabricated to examine the impact on phase noise of: 1.Base inductance (L B ) 2.Accumulation-mode nMOS varactors versus. MIM capacitors 3.Addition of L E 4.Operation on 2 nd harmonic versus. operation on fundamental.

Outline Motivation VCO and BPSK transmitter circuit topologies Design methodology for lowest phase noise VCOs  Experimental results Conclusions

Jazz Semiconductor’s commercial SBC  m BiCMOS process. Fabrication Technology Peak f T and f MAX near 155 GHz. NF min extracted from measured y-parameters [S. P. Voinigescu, et. al, JSSC 1997]

Varactor Q Characteristics

Microphotographs Family of 13 VCOs: Fundamental-Mode: (8) 35 GHz, (2) 60 GHz, Push-Push: (1) 70 GHz, (2) 120-GHz

Microphotographs (con’t) 65-GHz BPSK transmitter

35-GHz VCO Measurements Averaged Spectral Plots for 35-GHz VCO (L B = 100 pH, with L E ): (A) VCO(B) Fixed Freq. Oscillator

35-GHz VCO Measurements (con’t) Tuning and Output Power Characteristics:

Lowest Phase Noise Design Space Impact of:1. Base Inductance 2. Inductive Emitter Degeneration (L E )

60-GHz VCO Measurements Averaged Spectral Plots: (A) VCO(B) Fixed Freq. Oscillator

60-GHz VCO Measurements (con’t) Measurements over Temperature:

Push-Push VCO Measurements Spectral Plots: (a)70-GHz VCO P OUT > -14 dBm (b) 120-GHz VCO P OUT > -30 dBm

Push-Push VCO Measurements (con’t) Tuning Characteristics:

Si-Based mm-wave VCO Comparison Reference VCO L{f offset } (dBc/Hz) Tuning Range P DC (mW) P OUT (dBm) FOM *f T /f MAX (26-GHz) -87 at 100 KHz 15% ~ 40/50 GHz (BJT) (40-GHz) -97 at 1 MHz 15%  m (SOI) (43-GHz) -110 at 1 MHz 26% ~ 200 GHz (HBT) (77-GHz) -95 at 1 MHz 6% ~ 200 GHz (HBT) (63-GHz) pp -85 at 1 MHz 4%  m CMOS (150-GHz) pp -85 at 1 MHz 23% ~ 220 GHz (HBT) 35-GHz Osc at 1 MHz N/A ~ 155 GHz (HBT) 35-GHz VCO at 1 MHz 19% ~ 155 GHz (HBT) 60-GHz Osc at 1 MHz N/A ~ 155 GHz (HBT) 60-GHz VCO -103 at 1 MHz 13% ~ 155 GHz (HBT) 70-GHz VCO pp -94 at 1 MHz 21%128> -14< ~ 155 GHz (HBT) *FOM = L{f offset } - 20log(f osc /f offset ) + 10log(P DC /P OUT ) pp = push-push VCO

With DATA ( PRBS): BPSK Transmitter Measurements No DATA:

BPSK Transmitter Meas. (con’t) With DATA ( PRBS pattern):

Outline Motivation VCO and BPSK transmitter circuit topologies Design methodology for lowest phase noise VCOs Experimental results  Conclusions

Presented, with experimental validation, a systematic VCO design methodology for lowest phase noise. Compared to a MIM capacitor, accumulation-mode nMOS varactors degrades phase noise by 1-2 dB. Inductive degeneration lowers phase noise by 3-4 dB. Operation on 2 nd harmonic increases tuning range by 50% - at expense of lower P OUT First 65-GHz BPSK transmitter. Conclusions

Jazz Semiconductor, Gennum Corporation. Canadian Foundation for Innovation, Micronet, Canadian Microelectronics Corporation, NSERC. Marco Racanelli and Paul Kempf. Acknowledgements