Lecture 19 OUTLINE The MOSFET: Structure and operation Qualitative theory of operation Field-effect mobility Body bias effect Reading: Pierret 17.1, 18.3.4; Hu 6.1-6.5

Invention of the Field-Effect Transistor O. Heil, British Patent 439,457 (1935) In 1935, a British patent was issued to Oskar Heil. A working MOSFET was not demonstrated until 1955. EE130/230A Fall 2013 Lecture 19, Slide 2

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) An electric field is applied normal to the surface of the semiconductor (by applying a voltage to an overlying electrode), to modulate the conductance of the semiconductor. Drift current flowing between 2 doped regions (“source” & “drain”) is modulated by varying the voltage on the “gate” electrode. EE130/230A Fall 2013 Lecture 19, Slide 3 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.1

P. Packan et al., IEDM Technical Digest, pp. 659-662, 2009 Modern MOSFETs GATE LENGTH, Lg Metal-Oxide-Semiconductor Field-Effect Transistor: OXIDE THICKNESS, xo Intel’s 32nm CMOSFETs Gate Desired characteristics: High ON current Low OFF current Source Drain Substrate P. Packan et al., IEDM Technical Digest, pp. 659-662, 2009 Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode |GATE VOLTAGE| CURRENT “N-channel” & “P-channel” MOSFETs operate in a complementary manner “CMOS” = Complementary MOS VT EE130/230A Fall 2013 Lecture 19, Slide 4 4

N-channel vs. P-channel NMOS PMOS p-type Si N+ poly-Si n-type Si P+ poly-Si N+ N+ P+ P+ For current to flow, VGS > VT to form n-type channel at surface Enhancement mode: VT > 0 Depletion mode: VT < 0 Transistor is ON when VG=0V For current to flow, VGS < VT to form p-type channel at surface Enhancement mode: VT < 0 Depletion mode: VT > 0 Transistor is ON when VG=0V EE130/230A Fall 2013 Lecture 19, Slide 5

Enhancement Mode vs. Depletion Mode R. F. Pierret, Semiconductor Device Fundamentals, Fig. 18.18 Enhancement Mode Depletion Mode Conduction between source and drain regions is enhanced by applying a gate voltage A gate voltage must be applied to deplete the channel region in order to turn off the transistor EE130/230A Fall 2013 Lecture 19, Slide 6

CMOS Devices and Circuits CIRCUIT SYMBOLS N-channel MOSFET P-channel GND VDD S D CMOS INVERTER CIRCUIT VIN VOUT VOUT VIN VDD INVERTER LOGIC SYMBOL When VG = VDD , the NMOSFET is on and the PMOSFET is off. When VG = 0, the PMOSFET is on and the NMOSFET is off. And let’s move on to the FinFET based designs. We will start with the conventional double gated 6-T configuration. Here is our proposed layout. For gate WF adjustment, we are using angled implants. Therefore, from a process integration perspective, this type of layout prefers a single gate WF material. We are using 4.75eV gate WF here, which is close to the mid-gap. So our devices do have relatively high Vts, and that does reduce the cell leakage as I will mention later. From the layout, you see that we no longer need the big gap between N and P type devices. This is b/c for FinFETs, the substrate doesn’t define the transistor type, so we can have seamless transition from N-type to P-type active, avoiding the two contacts. So with 1 fin on the pull down devices, which is equivalent to having a beta ratio of 1, we can achieve 175mV of read margin. And the layout takes up about 0.36um2. So we do end up with a stable cell and less area compared to the bulk SRAM cell. EE130/230A Fall 2013 Lecture 19, Slide 7

“Pull-Down” and “Pull-Up” Devices In CMOS logic gates, NMOSFETs are used to connect the output to GND, whereas PMOSFETs are used to connect the output to VDD. An NMOSFET functions as a pull-down device when it is turned on (gate voltage = VDD) A PMOSFET functions as a pull-up device when it is turned on (gate voltage = GND) VDD A1 A2 AN Pull-up network input signals PMOSFETs only … F(A1, A2, …, AN) A1 A2 AN Pull-down network NMOSFETs only … EE130/230A Fall 2013 Lecture 19, Slide 8

CMOS NAND Gate VDD A B F A B A B F 1 EE130/230A Fall 2013 1 A B F A B EE130/230A Fall 2013 Lecture 19, Slide 9

CMOS NOR Gate VDD A B F B A A B F 1 EE130/230A Fall 2013 1 A B F B A EE130/230A Fall 2013 Lecture 19, Slide 10

CMOS Pass Gate A X Y Y = X if A A EE130/230A Fall 2013 Lecture 19, Slide 11

Qualitative Theory of the NMOSFET VGS < VT : depletion layer The potential barrier to electron flow from the source into the channel region is lowered by applying VGS> VT Inversion-layer “channel” is formed VGS > VT : VDS  0 VDS > 0 Electrons flow from the source to the drain by drift, when VDS>0. (IDS > 0) The channel potential varies from VS at the source end to VD at the drain end. EE130/230A Fall 2013 Lecture 19, Slide 12 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.2

MOSFET Linear Region of Operation For small values of VDS (i.e. for VDS << VGVT), where meff is the effective carrier mobility Hence the NMOSFET can be modeled as a resistor: EE130/230A Fall 2013 Lecture 19, Slide 13

Field-Effect Mobility, meff Scattering mechanisms: Coulombic scattering phonon scattering surface roughness scattering EE130/230A Fall 2013 Lecture 19, Slide 14 C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Figure 6-9

MOSFET Saturation Region of Operation VDS = VGS-VT VDS > VGS-VT When VD is increased to be equal to VG-VT, the inversion-layer charge density at the drain end of the channel equals 0, i.e. the channel becomes “pinched off” As VD is increased above VG-VT, the length DL of the “pinch-off” region increases. The voltage applied across the inversion layer is always VDsat=VGS-VT, and so the current saturates. ID VDS EE130/230A Fall 2013 Lecture 19, Slide 15 R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3

Ideal NMOSFET I-V Characteristics EE130/230A Fall 2013 Lecture 19, Slide 16 R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.4

Channel Length Modulation As VDS is increased above VDsat, the width DL of the depletion region between the pinch-off point and the drain increases, i.e. the inversion layer length decreases. If DL is significant compared to L, then IDS will increase slightly with increasing VDS>VDsat, due to “channel-length modulation” IDS VDS EE130/230A Fall 2013 Lecture 19, Slide 17 R. F. Pierret, Semiconductor Device Fundamentals, Figs. 17.2, 17-3

Body Bias When a MOS device is biased into inversion, a pn junction exists between the surface and the bulk. If the inversion layer contacts a heavily doped region of the same type, it is possible to apply a bias to this pn junction. N+ poly-Si VG is biased so that surface is inverted n-type inversion layer is contacted by N+ region If a bias VC is applied to the channel, a reverse bias (VB-VC) is applied between the channel and body + + + + + + + + SiO2 - - - - - N+ - - - - p-type Si EE130/230A Fall 2013 Lecture 19, Slide 18

Effect of VCB on fS, W and VT Application of a reverse body bias  non-equilibrium  2 Fermi levels (one in n-type region, one in p-type region) are separated by qVBC  fS is increased by VCB Reverse body bias widens W, increases Qdep and hence VT EE130/230A Fall 2013 Lecture 19, Slide 19